SUMMARYWe analyze the existing bi-level IIR-based bit-stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi-level design to tri-and quad-level architectures that offer better signal-to-noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR-based bit-stream multipliers. Useful design guidelines are subsequently drawn.
Quad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quadlevel BSSP offers better performance than their biand tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs.
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