On IIR‐based bit‐stream multipliers

Ng, Chiu-Wa; Wong, Ngai; So, Hayden Kwok-Hay; Ng, Tung-Sang

doi:10.1002/cta.623

Cited by 2 publications

(7 citation statements)

References 25 publications

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“…The work that was commenced by the authors in [22] and progressed by the ones in [8,24] has been reported by many, such as in [1-4, 7, 25-28]. More recently sigma-delta modulation based bit-stream adder and multiplier modules have been described in [29,30].…”

Section: Sigma-delta Modulation Based Fast Filtersmentioning

confidence: 99%

“…Bit-stream arithmetic modules with bi-, tri-, and quad levels are described in [30,32,47,48]. In these cases, hardware implementation of the arithmetic modules is done in Xilinx Virtex-5 using two's complement representation.…”

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

“…Unlike [32,47,48], in [30] an existing IIR low pass filter ΣΔM is utilized to generate the input bit-stream and the design has been analysed to characterise the selection of the ΣΔM design parameter (i.e., K, shown in Figure 11). The design was extended to tri-and quad level and compared with the bilevel ΣΔM.…”

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

“…The design was extended to tri-and quad level and compared with the bilevel ΣΔM. The noise performance was simulated for all three types of multipliers and it was found that trilevel design has a performance gain of 11.2 dB over the bilevel design, while the quad-level design has about a further 8.8 dB gain over the trilevel design [30].…”

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

“…These results indicate that the bilevel design is more resource efficient than either of the tri-and quad level and provides a higher performance at the cost of lower noise suppression and vice versa. However, this Figure 11: First order digital sigma-delta modulator [30].…”

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

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Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

2012

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In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based areaperformance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance.

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Section: Sigma-delta Modulation Based Fast Filtersmentioning

confidence: 99%

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

Section: Vlsi Analysis Of σδM Based Bit-stream Circuitsmentioning

confidence: 99%

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Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

2012

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A Generalized One-Bit Control System Using a $\Delta\Sigma$ -Quantizer

et al. 2019

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This paper presents the use of a delta-sigma quantizer for generalized one-bit control processing. An equivalent control strategy based on sliding-mode control is employed to derive the necessary condition for the convergence of the proposed one-bit control system in both the continuous-time and discrete-time domains. Under the convergence condition, the binary signals generated by delta-sigma quantizers in the one-bit control system effectively replace their counterpart signals in conventional control systems. This enables a significant reduction in the number of multipliers and overall hardware cost for computing the control laws in one-bit control systems. Our result is applied to design a multiplier-less onebit generalized proportional and integral controller for the position control of an experimental prototype of a DC motor. An implementation of the one-bit control system is carried out using an FPGA platform to demonstrate the behavior of one-bit generalized proportional and integral controller and compare the results with the standard in terms of implementation efficiency. The results of the simulation and experiment show that the one-bit generalized proportional and integral controller effectively controls the system and achieves the desired specifications. At the same time, the proposed one-bit control system consumes significantly fewer hardware resources than the standard control system. INDEX TERMS One-bit control processing, delta-sigma quantizer, quantized control systems, equivalent control, sliding mode, generalized proportional and integral.

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On IIR‐based bit‐stream multipliers

Cited by 2 publications

References 25 publications

Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

A Generalized One-Bit Control System Using a $\Delta\Sigma$ -Quantizer

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