With the progress of science and technology, the image resolution of monitoring systems is entered the Full-HD (High Definition) era. The Full-HD refers to resolution of 1920X1080 (1080p), and the image refresh frequency is 30fps (Frames Per Second). Therefore, this thesis uses FPGA as image system processor, as well as uses AFE to implement a camera module. First, the dual-channel serial signal from AFE is converted into single-channel parallel signal, and the image is processed following our image processing procedure before charting and export. The image processing procedure includes AEC, auto color balance, color filter array interpolation, color correction, noise filter, gamma correction and dynamic range correction. Our algorithm counts information instantly, and calculates better correcting function content, so that we can display the brighter and darker parts of images clearly in different environments. Compared with a part of CCD digital cameras on the market, our ISP has better performance in SNR. Finally, the AWB mean error of our ISP design is less than 0.02%, it is difficult to be perceived by human eyes.
One of the key technologies for high-resolution camera is the analog front end (AFE) design, which is between the lens and image system process (ISP). The 2 major evaluations of AFE are to evaluate the noise and the ratio between the RGB pixels. Hence, based on the charge coupled device (CCD) image sensor, we present our proposed AFE design to evaluate the CCD noise of the output image with a lower dark current. Our proposed AFE board design is to employee the 1080p (1920×1080) CCD image sensor and its corresponding timing controller with the digital-analog converter (ADC). Our results indicate that our design has the high performance among 6 different digital brands in the low noise applications. Moreover, the CCD sensors with the different resolutions can be installed within the same socket of our AFE board, which can also simultaneously support 3 types, Bayer, Truesense, and Black/White, color filter array.
In a mobile ad-hoc network, MANET, designing a security routing protocol is an important issue since the mobile nodes and wireless medium are prone to be attacked. However, most of wireless routing protocols concentrated on how to reduce the data transmission time and energy consumption. Wireless routing paths in MANET may be broken or fabricated by attacking. Hence, sending data packets to the destination may failure. For defending the active black hole attacks and the passive fabricated routing attacks, we proposed a preventive security mechanism based on ad-hoc on-demand distance vector routing (AODV), called PSM-AODV. PSM-AODV modified some field in RREQ, RREP, and RERR packets based on AODV. PSM-AODV thus may defend the possible black hole and fabricated routing attacks. Simulation results showed that PSM-AODV could promote the packet delivery rate based on little overhead in control packets.
License plate recognition systems can be classified into several categories: systems with single camera for motionless vehicle, systems with single camera for moving vehicle, and systems with multiple cameras for moving vehicles on highways (one camera for each lane). In this paper we present an innovative system which can locate multiple moving vehicles and recognize their license plates with only one single camera. Obviously, our system is highly cost effective in comparison with other systems. Our system has license plate localization success rate 94% and license plate recognition success rate 88%. These success rates are pretty satisfiable considering the system is working on fast moving vehicles on highway.
In the ECC, scalar multiplication represents the core operation of the system. In recent years, the circuit architecture of triple processor cores or greater has been addressed in the domestic and international literature. A parallel processing concept is mainly used in this type of framework to accelerate circuit operation. In the present study, equation calculation and circuit design were employed to integrate the pipeline architecture and the parallel processing architecture and further propose an elliptic curve scalar multiplier for dual processor cores. In addition, a Xilinx XC5VLX110T FPGA was used to verify the accuracy and performance of circuit functions. The maximum frequency was 173 MHz, the number of LUTs was 14999 slices, and the time to accomplishing one scalar multiplication was only 8.8s. Compared to architectures described in recent reports, the architecture presented was faster and effectively reduced the square measure by 28%.
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