Design and Implementation of a Low-Cost Scalar Multiplier-on-Chip for Elliptic Curve Cryptosystem

Abstract

In the ECC, scalar multiplication represents the core operation of the system. In recent years, the circuit architecture of triple processor cores or greater has been addressed in the domestic and international literature. A parallel processing concept is mainly used in this type of framework to accelerate circuit operation. In the present study, equation calculation and circuit design were employed to integrate the pipeline architecture and the parallel processing architecture and further propose an elliptic curve scalar multiplier for dual processor cores. In addition, a Xilinx XC5VLX110T FPGA was used to verify the accuracy and performance of circuit functions. The maximum frequency was 173 MHz, the number of LUTs was 14999 slices, and the time to accomplishing one scalar multiplication was only 8.8s. Compared to architectures described in recent reports, the architecture presented was faster and effectively reduced the square measure by 28%.