Background Premature rupture of membranes (PROM) may cause intra-uterine infection and fetal death. A diagnostic tool that is non-invasive, specific and quick is needed to predict PROM. Human chorionic gonadotrophin (hCG), a-fetoprotein (AFP) and interleukin 6 (IL-6), which are present in vaginal fluid, were reported to be potential markers for PROM but have not yet been used in the clinic. This study was designed in a daily routine semi-emergency setting to evaluate the clinical practicability of using these markers in diagnosing PROM.
We present in this article an external memory algorithm, called disk SA-IS (DSA-IS), to exactly emulate the induced sorting algorithm SA-IS previously proposed for sorting suffixes in RAM. DSA-IS is a new diskfriendly method for sequentially retrieving the preceding character of a sorted suffix to induce the order of the preceding suffix. For a size-n string of a constant or integer alphabet, given the RAM capacity ((nW ) 0.5 ), where W is the size of each I/O buffer that is large enough to amortize the overhead of each access to disk, both the CPU time and peak disk use of DSA-IS are O(n). Our experimental study shows that on average, DSA-IS achieves the best time and space results of all of the existing external memory algorithms based on the induced sorting principle.
When the Internet is evolving from IPv4 to IPv6, there is a need in practice for route lookup algorithms that can simultaneously support IPv4 and IPv6 packets. A scalable pipeline routing architecture for route lookups of IPv4/IPv6 packets using a prefix trie is studied in this work. In this routing architecture, a routing table is mapped into an index table and a number of prefix tries. Each prefix trie is further divided into multiple subtries, where two copies are maintained for each subtrie. Specifically, each subtrie has two copies rooted in two different memory blocks. For each copy of a subtrie, the root node is stored in a randomly selected memory block and the other descendant nodes are cyclically stored in the subsequent memory blocks in a manner of one level per block. The scheduling problem in such an architecture is modeled as bipartite matching between packets and memory blocks. For performance evaluation, extensive simulation experiments have been conducted for typical IPv4 and IPv6 corpora. The simulation results indicate that this routing architecture can achieve high system's throughputs under both IPv4 and IPv6 traffic loads.Index Terms-IPv4/IPv6, route lookup, pipeline architecture, prefix trie, bipartite matching.
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