The metal-insulator-metal (MIM) capacitor for analog and rf applications has been developed with ZrO2∕Al2O3∕ZrO2 laminate as the dielectric. The high capacitance density of 21.54fF∕μm2 can be achieved due to the tetragonal ZrO2 which makes the higher dielectric constant of 38.7. This MIM capacitor also demonstrates the quadratic voltage coefficient of 2443ppm∕V2 and the good leakage current of 2.11×10−6A∕cm2 at 2V which is ascribed to the inserted Al2O3. Since the Schottky emission is suggested as the major dielectric conduction mechanism, a further reduced quadratic voltage coefficient and leakage characteristic can be realized by using a high work-function electrode. The combination of the promising electrical properties and the desirable process integration renders this structure highly suitable for advanced MIM capacitors.

Pb(Zr 0.52 Ti 0.48 ) O 3 (PZT) thin films were synthesized on a sapphire substrate for application as planar optical waveguide devices using a metalorganic decomposition (MOD) process. Pyrochlore phase, which always forms preferentially when the PZT thin films (∼200 nm) are deposited on a sapphire substrate directly, has been effectively suppressed by using a SrTiO3 (STO) film (∼190 nm) as a buffer layer. The PZT/sapphire thin films have a significantly larger refractive index than the STO/sapphire ones: nPZT=2.2012 and nSTO=2.0639 (at 632.8 nm) by prism coupling measurement and nPZT′=2.215 and nSTO′=2.084 (at 632.8 nm) by optical transmission spectroscopic measurement. The STO layer cannot only serve as buffer layer for enhancing the crystallization kinetics of the subsequently deposited PZT thin films, but can also serve as cladding layer in a ridge-type planar waveguide, which uses PZT thin film as core materials.

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PZT thin films are deposited on SiO 2 /Si substrate by metallo-organic decomposition (MOD) process, using SrTiO 3 (STO) as buffer layer for textured growth. The STO layers deposited on SiO 2 /Si substrate by pulsed laser deposition process show (100)/(200) preferred orientation, whereas the STO buffer layer deposited on silica substrate using spin-coating technique show random orientation behavior. The use of STO as buffer layers enhanced the crystallization and the preferred orientations of the PZT films. The PZT on STO buffered SiO 2 /Si substrates thus obtained possess high refractive index, (n) PZT/STO = 2.1159, and are of good enough quality for optical waveguide applications.

Si nanocrystal with a high density of 5.1 ϫ 10 11 cm −2 and an average size of 7.2 nm has been achieved on the NH 3 -nitrided tunnel oxide, and the density is higher than that formed on the untreated tunnel oxide by a factor of 3.2. The higher density obtained by this technique is attributed to the lower activation energy for the Si nanocrystal nucleation growth on the nitrogen-containing surface of the nitrided tunnel oxide. The memory device with such a high nanocrystal density demonstrates a 1.79 V threshold voltage shift by programming at 10 V for 10 ms and a negligible memory window degradation up to 10 6 program/erase cycles. The good charge storage capability is evidenced by an extrapolated 10 year memory window of 0.92 V at 150°C.Because of the widespread adoption in consumer electronics and the growing demand in personal computer applications for nonvolatile memory, it has drawn intensive research interest in further scaling the memory cell size and reducing the operation voltage of the current floating-gate-based nonvolatile memory. With the mutually isolated and discrete charge trapping sites, nanocrystal memory has been regarded as one of the most promising flash memory technologies due to its better scalability, lower program/erase voltage, and enhanced endurance performance. In addition, compared with polycrystalline Si-oxide-nitride-oxide-Si ͑SONOS͒, the other widely investigated charge-trapping memory, it reveals several merits in more controllable trap sites and larger trapping probability. 1 Owing to the fully compatible process of incumbent ultralarge-scale integration technology, Si nanocrystal memory has received much attention for years. 2-12 Nevertheless, Si nanocrystal memory still exhibits a limited retention and a small memory window that would restrict its potential application for nonvolatile memory. To address this issue, many research groups have proposed structures including highpermittivity interpoly dielectric, 2 highly field-sensitive nitrideoxide-nitride as the tunnel barrier, 3 doubly stacked Si nanocrystal, 4 surface-nitrided Si nanocrystal, 5 and hybrid Si nanocrystal Si nitride memory. 6 However, few reports discuss the approach to form highdensity Si nanocrystal, which is essential to further boost the program/erase speed and memory window. Si nanocrystal fabricated by ion implantation of excess Si into the oxide and subsequent thermal annealing is a straightforward method to control the nanocrystal density; 7 unfortunately, it would compromise the tunnel oxide quality. Although high-density Si nanocrystal formed by low-energy SiH 4 plasma immersion ion implantation seems to be practically feasible, 8 it necessitates a different type of ion implantation tool to implement. In this article, with the existent standard process tools in a mass production fabrication, high-density Si nanocrystal formation has been achieved on the appropriately nitrided tunnel oxide. The large memory window with a good endurance performance from the electrical characterization of the memory device...