Pursuit of lower k 1 for pushing the resolution limit becomes one of the most demanding tasks to meet stringent patterning requirements in next generation lithography. Particularly, the patterning of densely packed array devices with periodic and symmetric features is among the most challenging missions to enable high density memory chips to quickly move forward as projected by Moore's Law. As dictated by the physical limitation of optical system design, current immersion scanners are not capable of reliably printing feature sizes down to sub-40nm regime unless resorting to high index fluids or other effective Resolution Enhancement Techniques (RETs). Fortunately, recent prosperous progress in double patterning technique seems to give realistic hope as a straightforward bridge between the current immersion scanners [1] and the relatively immature EUV scanners [2]. State-of-the-art double patterning technique [3] includes the well known LLE (Litho-Litho-Etch) [4], LELE (Litho-Etch-Litho-Etch) [5], self-aligned [6] and other approaches [7].Among them the self-aligned approach is regarded as more appropriated for mass production of high density arrays due to less concerned of overlay budget [8]. In this paper, we studied the integrated lithography performance of one innovative self-aligned double patterning scheme for the demonstration of sub-40nm capability by the use of the most advanced 193nm dry scanner. In addition, silicon containing bottom reflective coating (BARC) was employed for the CD trimming in order to optimize the lithography & etch process windows [9]. A 37.5nm half-pitch L/S memory array with well controlled line edge roughness (LER) was successfully demonstrated in this work by the above mentioned selfaligned spacer approach. The equivalent k 1~0 .146 was readily achieved without too much complex integration, which is especially suitable for the future high density memory arrays as in FLASH or DRAM.
Rob Hovsapian spent almost 20 years working for General Dynamics, TRW, and Northrop Grumman. Currently, he serves as an Associate Scholar Scientist/Faculty, Instructor of record for a senior capstone design course, for the Mechanical Engineering Department, and a Program Manager at the Center for Advanced Power Systems for the Electric Ship Research and Development Consortium (ESRDC) for the Office of Naval Research. He has been responsible for the successful establishment/deployment of several flexible manufacturing startup facilities globally, working on multiple continents and with many cultures, which produced sophisticated defense electronics equipment, complex automotive systems, and advanced semiconductors. Hovsapian has personally been recognized nationally for his process improvement activities in manufacturing excellence. He received his master's of science and doctorate in mechanical engineering from Florida State University.
In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.
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