Spacer double patterning technique for sub-40nm DRAM manufacturing process development

Abstract

Pursuit of lower k 1 for pushing the resolution limit becomes one of the most demanding tasks to meet stringent patterning requirements in next generation lithography. Particularly, the patterning of densely packed array devices with periodic and symmetric features is among the most challenging missions to enable high density memory chips to quickly move forward as projected by Moore's Law. As dictated by the physical limitation of optical system design, current immersion scanners are not capable of reliably printing feature sizes down to sub-40nm regime unless resorting to high index fluids or other effective Resolution Enhancement Techniques (RETs). Fortunately, recent prosperous progress in double patterning technique seems to give realistic hope as a straightforward bridge between the current immersion scanners [1] and the relatively immature EUV scanners [2]. State-of-the-art double patterning technique [3] includes the well known LLE (Litho-Litho-Etch) [4], LELE (Litho-Etch-Litho-Etch) [5], self-aligned [6] and other approaches [7].Among them the self-aligned approach is regarded as more appropriated for mass production of high density arrays due to less concerned of overlay budget [8]. In this paper, we studied the integrated lithography performance of one innovative self-aligned double patterning scheme for the demonstration of sub-40nm capability by the use of the most advanced 193nm dry scanner. In addition, silicon containing bottom reflective coating (BARC) was employed for the CD trimming in order to optimize the lithography & etch process windows [9]. A 37.5nm half-pitch L/S memory array with well controlled line edge roughness (LER) was successfully demonstrated in this work by the above mentioned selfaligned spacer approach. The equivalent k 1~0 .146 was readily achieved without too much complex integration, which is especially suitable for the future high density memory arrays as in FLASH or DRAM.

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

“…However, the overall simulation time is already not burdensome. 4 Notice that interconnects assigned to mask1 or mask2 have twice the pitch with respect to the final interconnect pitch. It is this pitchdoubling feature that helps double patterning achieve printability of finer-pitch interconnects than a traditional process.…”

“…Interconnects with the number "1" and "2" on them will be printed using mask1 and mask2, respectively, whereas both would have been on the same mask in a traditional process. 4 In Figure 3(a), we assume that the interconnects printed using mask2 are shifted by S due to overlay error in a positive photoresist DE or DP process. 5 S is assumed positive in the figure.…”

“…Finally in SDP, one lithography and one etch step are followed by spacer formation, oxide deposition, chemical-mechanical polishing and a second etch. SDP is seen as a very viable option for regular patterns such as poly gates [4] as well as bitlines [5] of a memory design. However, SDP requires additional process steps, including chemical-mechanical polishing which may be costly and difficult to optimize, and also requires a trim mask to remove undesired spacer (trimming) or generated patterns (repairing) when implementing irregular patterns [4], [6].…”

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

“…It consists of an inexpensive and non-critical trim-exposure cycle (resist coat-expose-develop) and removal of hardmask corresponding to extra printed features before the final etch. The trim exposure is a mature and well-known method used in many patterning techniques such as SADP [9,10], alternating phase-shift mask [11], and subtractive-litho patterning [12,13]. It was recently employed to trim-away printing assist features (PrAF) introduced to enhance the resolution of conventional single patterning [14].…”

Single-mask double-patterning lithography

“…Trim-exposure is a mature and well-known method used in many patterning techniques such as double-patterning with spacer [14,15], alternating phase-shift mask [13], and subtractive-litho patterning [17,18]. It was recently employed to trim-away printing assist features (PrAF) introduced to enhance the resolution of conventional single patterning [16].…”