ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng, Andrew B.; Li, Bin; Peh, Li-Shiuan; Samadi, Kambiz

doi:10.1109/date.2009.5090700

Cited by 543 publications

(340 citation statements)

References 41 publications

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“…Included with the software release are algorithms for generating a mesh and a min-cut partitioning method (hierarchical star) similar to that of [6]. We modified COSI to incorporate the Orion 2.0 router and wire models [23], and also made a number of other changes to COSI to improve its operation and result reporting.…”

Section: Synchronous Network Generationmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

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Section: Synchronous Network Generationmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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“…We conducted several experiments using a modified version of GEM5 as an appropriate cycle-accurate simulator (http: //gem5.org), a modified version of McPAT [17] and Orion [13] detailed models for cores and routers power consumption estimates, and the widely used HotSpot thermal model [24] to generate chip temperature map. The reference architecture we target is an Alpha21364 network architecture [20], that is used in real Web-servers and Data-centre contexts; commercial examples exist for this kind of architecture, based on the Alpha21264 processor core.…”

Section: A Experimental Setup and Methodology Evaluationmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-Multi-core architectures are a promising paradigm to exploit the huge integration density reached by highperformance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM techniques.

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“…To enable power and thermal analysis, HORNET combines a dynamic power model based on ORION 2.0 [18] with a leakage power model; an accurate thermal model uses HOTSPOT 5.0 [19]. At runtime, various system configuration parameters (buffer sizes, port counts, etc.)…”

Section: B Power and Thermal Modelingmentioning

confidence: 99%

Scalable, accurate multicore simulation in the 1000-core era

Lis

Ren

Cho

et al. 2011

(Ieee Ispass) Ieee International Symposium on Performance Analysis of Systems and Software

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Abstract-We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued wormhole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 11×.Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, and parameters driving power and thermal effects. A highly parametrized table-based NoC design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. HORNET can run in network-only mode using synthetic traffic or traces, directly emulate a MIPS-based multicore, or function as the memory subsystem for native applications executed under the Pin instrumentation tool.HORNET is freely available under the open-source MIT license at http://csg.csail.mit.edu/hornet/.

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ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Cited by 543 publications

References 41 publications

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Thermal/performance trade-off in network-on-chip architectures

Scalable, accurate multicore simulation in the 1000-core era

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