Scalable, accurate multicore simulation in the 1000-core era

Lis, Mieszko; Ren, Pengju; Cho, Myong Hyon; Shim, Keun Sup; Fletcher, Christopher W.; Khan, Omer; Devadas, Srinivas

doi:10.1109/ispass.2011.5762734

Cited by 45 publications

(31 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To simulate accurate behavior of a NUCA cache architecture and memory network we integrate it with HORNET [8] NoC simulator that simulates NoC architectures with high accuracy and detailed latency, network traffic, and power analysis. To enable power analysis, HORNET combines a dynamic power model based on ORION [23] with a leakage power model.…”

Section: Methodsmentioning

confidence: 99%

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

BanaiyanMofrad

Homayoun

Kontorinis

et al. 2013

2013 International Green Computing Conference Proceedings

View full text Add to dashboard Cite

Section: Methodsmentioning

confidence: 99%

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

BanaiyanMofrad

Homayoun

Kontorinis

et al. 2013

2013 International Green Computing Conference Proceedings

View full text Add to dashboard Cite

“…✓ ✓ microarchitecture, [Hsieh et al 2011] power and thermal Lis et al ✓ ✓ ✓ many-core processors, (HORNET) [Lis et al 2011] (simple) mainly NoC interconnect Bartolini et al…”

Section: Hsieh Et Al (Sst)mentioning

confidence: 99%

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Zoni

Fornaciari

2015

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multicore revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

show abstract

“…Lis et al [20] is meant to simulate large-scale architectures, and exploits parallel simulation on physical hardware with particular emphasis on the on-chip network. Although the framework enables power-performance trade-off analysis, it is missing a complete asynchronous on-chip network model, hence it is not possible to explore different GALS configurations for the interconnect, as well as the simulation of Dynamic Frequency Scaling driven by high level policies.…”

Section: Simulation Frameworkmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

View full text Add to dashboard Cite

a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

show abstract

Scalable, accurate multicore simulation in the 1000-core era

Cited by 45 publications

References 27 publications

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Contact Info

Product

Resources

About