Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-m-thick layer. This 3D technology is extremely well suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-m-wide through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explained by considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material layers of the 3DIC stack. We also show that the back metal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.Index Terms-3D technology, fully depleted, heavy ions, single event effects (SEEs), single event transient (SET), SOI.
We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
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