SET Characterization in Logic Circuits Fabricated in a 3DIC Technology

Abstract

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-m-thick layer. This 3D technology is extremely well suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-m-wide through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explained by considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material layers of the 3DIC stack. We also show that the back metal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.Index Terms-3D technology, fully depleted, heavy ions, single event effects (SEEs), single event transient (SET), SOI.

Geant4 simulation of proton-induced single event upset in three-dimensional die-stacked SRAM device*

“…[3] It is also because of the broad application prospects of 3D-IC in the aerospace field, its irradiation effect has also received the researcher's attention. [4][5][6][7][8][9][10][11] Zhang et al made the first significant attempt to characterize the microarchitecture soft error vulnerabilities across the stacked chip layers under 3D integration technologies. [4] They showcased that alpha particles induced by package material only affect the top layers of the 3D-IC because the outer layers have a shielding effect on inner layers.…”

“…In 2011, Gouker et al conducted a series of studies on single event upset (SEU) and single event transient for 3D-IC fabricated in Silicon-On-Insulator technology. [5,6] Since heavy ions have a higher linear energy transfer (LET) than proton, more energy can be deposited in the device, and more electronhole pairs are generated, so most of the researches have focused on single event effect induced by heavy-ion. For example, Cao X et al conducted a Geant4 simulation on heavy ions induced SEU for 3D integrated SRAM.…”

Evaluation Method of Heavy-Ion-Induced Single-Event Upset in 3D-Stacked SRAMs

“…Although the study of Zeng et al indicated that the leakage current of through-silicon via (TSV) metal-oxide-semiconductor (MOS) structure would increase after exposure to gamma ray irradiation [6], it is important and necessary to consider the effect of radiation on the reliability of TSV-based applications under radiation conditions. Moreover, the single-event effects (SEE) in the 150-nm SOI and bulk silicon 3D static random-access memory (SRAM) circuits were evaluated by Gouker et al (proton, neutron, and heavy ion) [7,8] and Uznanski et al (proton) [9]. The experimental results indicated that the radiation effects on 2D and 3D SRAMs fabricated using the same techniques have a similar response, but high-Z materials such as tungsten can have an impact on the SEE sensitivity of the lower tiers.…”

“…The experimental results indicated that the radiation effects on 2D and 3D SRAMs fabricated using the same techniques have a similar response, but high-Z materials such as tungsten can have an impact on the SEE sensitivity of the lower tiers. Owing to the back metal layer available on the upper tiers in the SOI complementary metal-oxide-semiconductor (CMOS) tier stacked circuit, it can be used as a back gate to tune the field-effect transistor (FET) current drive and attenuate the Single-event transient (SET) pulse width and cross-section (CS) [8]. Furthermore, the impacts of the various energies of proton and heavy-ion irradiation on the 90-nm and 55-nm 3D bulk silicon IC technology were also evaluated by Gupta et al [10] and Cao et al [11].…”