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An integration scheme for realizing strained n-channel metal-oxide-semiconductor field-effect transistors ͑nFETS͒ with embedded silicon-carbon ͑e-Si:C͒ source/drain ͑S/D͒ stressors formed in close proximity to the channel was demonstrated. The stressors are termed channel-proximate ͑CP͒ Si:C S/D stressors, whose proximity to the channel improves their effectiveness in contributing to tensile strain in the channel region. Numerical simulation was performed using the finite-element method to assess the strain enhancement due to CP Si:C S/D. Key process development and material characterization were performed to understand the interaction between dopants and substitutional carbon concentration C sub . Unstrained control nFETs, nFETs with conventional Si:C S/D formed after spacers, and nFETs with CP Si:C S/D were fabricated. The nFET with CP Si:C S/D stressors achieved a drive current I on enhancement of ϳ19 and ϳ8% over unstrained nFET and nFET with conventional Si:C S/D, respectively. The impact of channel orientation on I on enhancement was also investigated.Strained silicon metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ have been widely adopted in integrated circuit manufacturing. For n-channel metal-oxide-semiconductor fieldeffect transistors, or nFETs, stress memorization technique ͑SMT͒ 1,2 and silicon nitride etch-stop layer with high tensile stress 3,4 have been employed to induce lateral tensile strain in the silicon channel for enhancement of carrier mobility and drive current I on . Recently, the embedded silicon-carbon ͑e-Si:C͒ source/drain ͑S/D͒ stressor has gained attention as another viable option for strain engineering of silicon nFETs. 5-16 The e-Si:C S/D stressor can be formed using selective epitaxial growth, 5-10,13-15 or by ion implantation of carbon followed by solid-phase epitaxy ͑SPE͒. 11,12 With the scaling down of the gate pitch for higher circuit density, the effective stress in the channel due to various strain engineering schemes generally decreases. As a result, performance degradation associated with stress loss due to pitch scaling can be substantial. 17,18 To maintain or increase the strain effects due to the S/D stressor, solutions such as increasing the substitutional carbon concentration in Si:C S/D, increasing the thickness of the S/D stressor, 19,20 or alteration of the mechanical boundary conditions, e.g., removal of spacers, 21 to increase the channel stress have been demonstrated. To enable further pitch reduction with minimal performance compromise, new techniques to maintain or further enhance the strain in the transistor channel region will be highly desirable.In this paper, we demonstrate an integration scheme for realizing strained nFETs with enhanced strain effects by deploying Si:C S/D stressors in close proximity to the channel, hereafter referred to as channel-proximate ͑CP͒ Si:C S/D stressors. This paper focuses on Si:C S/D formed using carbon implant and SPE and its integration adjacent to the channel. Numerical simulation using the finiteelement meth...

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Introduction. Embedded Silicon-Carbon (e-Si:C) source/drain (S/D) stressor enhances n-FET drive current I on , and is a much-needed strain engineering option for future logic technologies. However, carbon in Si reduces dopant activation and increases the external resistance R EXT and contact resistance R CSD . As R EXT is a significant component of the total source-to-drain resistance in aggressively scaled MOSFETs [1], there is an immense interest in alleviating issues related to high R EXT and R CSD . In this paper, we report a novel scheme of reducing the electron barrier height ( B