A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).
We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CPtrees can flexibly pack movable macros toward corners or preplaced macros along chip boundaries circularly to optimize macro positions/orientations for better wirelength and routing congestion. Unlike previous macro placers that often consider only the interconnections among macros, we develop a routability-aware wirelength model to fast estimate the wirelength among macros and standard cells and to consider macro porosity effects for better routability. Compared with leading academic mixed-size placers, experimental results show that our algorithm can achieve the shortest routed wirelength for industrial benchmarks.
Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic without changing the functionality. Despite significant efforts spent on sequential optimization since 1980's, there are few works discussed its performance in an endto-end design flow. The retiming algorithms were mostly evaluated at the logic level. However, it turns out that the retiming results at logic level could be significantly different than evaluating the physical level. This paper provides the findings of how retiming algorithms perform in an end-to-end industrial design flow, with seven industry designs taken from a recent 14nm microprocessor. Experiments are conducted with several complete industrial design flows. The evaluations are made at the end of the physical design flow. The experimental results show that the performance (design quality) of the retiming algorithms vary on the designs. Based these experimental results, we discover a feature that describes the retiming potentials of sequential designs. This model successfully forecast whether the given industrial designs could be significantly improved by retiming in an end-to-end design flow, regarding timing, area, and power.
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