Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

Kuo, Yun-Chih; Huang, Chau-Chin; Chen, Shih-Chun; Chiang, Chun-Han; Chang, Yao‐Wen; Kuo, Sy‐Yen

doi:10.1109/tcad.2020.2968892

Cited by 20 publications

(10 citation statements)

References 27 publications

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“…RippleFPGA [23] GPlace [7] UTPlaceF [5] elfPlace [13] FTPlace [20] GPlace 3.0 [24] RippleFPGA Clock-Aware [11] UTPlaceF 2.0&2.X [9], [10] NTUfPlace [15] Lin et al [ total number of clock nets whose bounding boxes intersect with the clock region. The half-column constraint limits the number of clock nets within the half-column to a maximum of 12.…”

Section: Placermentioning

confidence: 99%

“…TABLE I summarizes the characteristics of the published state-of-the-art FPGA placers. In recent years, modern FPGA placers mainly resort to quadratic programming-based approaches [4]- [12] and nonlinear optimization-based approaches [13]- [15] for the best trade-off between quality and efficiency. Among them, the current state-of-the-art quality is achieved by nonlinear approaches elfPlace [13] and NTUfPlace [15], whose instance density models are derived from a multi-electrostatics system and a hand-crafted bellshaped field system.…”

Section: Problem Formulationmentioning

confidence: 99%

“…Experiments on ISPD 2017 contest benchmarks demonstrate 14.2%, 11.7%, 9.6%, and 7.9% improvement in routed wirelength, compared to the recent cutting-edge FPGA placers [9]- [11], [15], respectively. Our placer also supports GPU acceleration and gains 1.45-6.58× speedup over the baselines.…”

Section: Introductionmentioning

confidence: 99%

“…SA-based approaches like the widely-adopted academic tool VPR [3] can achieve good results on small designs, but suffer from poor scalability on large designs. Recent studies have shown that analytical approaches [4]- [15] can achieve the best trade-off between quality and runtime. Thus modern FPGA placers mainly adopt analytical approaches in academia and industry.…”

Section: Introductionmentioning

confidence: 99%

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Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

Mai

Meng

et al. 2022

Proceedings of the 59th ACM/IEEE Design Automation Conference

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When modern FPGA architecture becomes increasingly complicated, modern FPGA placement is a mixed optimization problem with multiple objectives, including wirelength, routability, timing closure, and clock feasibility. Typical FPGA devices nowadays consist of heterogeneous SLICEs like SLICEL and SLICEM. The resources of a SLICE can be configured to {LUT, FF, distributed RAM, SHIFT, CARRY}. Besides such heterogeneity, advanced FPGA architectures also bring complicated constraints like timing, clock routing, carry chain alignment, etc. The above heterogeneity and constraints impose increasing challenges to FPGA placement algorithms.In this work, we propose a multi-electrostatic FPGA placer considering the aforementioned SLICEL-SLICEM heterogeneity under timing, clock routing and carry chain alignment constraints. We first propose an effective SLICEL-SLICEM heterogeneity model with a novel electrostatic-based density formulation. We also design a dynamically adjusted preconditioning and carry chain alignment technique to stabilize the optimization convergence. We then propose a timing-driven net weighting scheme to incorporate timing optimization. Finally, we put forward a nested Lagrangian relaxation-based placement framework to incorporate the optimization objectives of wirelength, routability, timing, and clock feasibility. Experimental results on both academic and industrial benchmarks demonstrate that our placer outperforms the state-of-the-art placers in quality and efficiency.

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Section: Placermentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

Mai

Meng

et al. 2022

Proceedings of the 59th ACM/IEEE Design Automation Conference

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“…The connectivity-based partitioning/clustering algorithms used by AMF-Placer 1.0 [33] and other previous works [9] [41] do not consider timing factors in partitioning.…”

Section: A Initial Floorplanningmentioning

confidence: 99%

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

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To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

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An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs

Li,

Zhu,

et al. 2024

Integration

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Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

Cited by 20 publications

References 27 publications

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs

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