Routability-driven placement for hierarchical mixed-size circuit designs

Abstract

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).

Placement: From Wirelength to Detailed Routability

“…In NTUPlace [50], routability is optimized by minimizing net congestion in bins. In each bin, a term called Routable area is obtained, which is the supply in routing resource in the bin.…”

Routability-Driven Blockage-Aware Macro Placement

“…Though the macro placement areas in Figure 13(a) and Figure 13(b) are the same, the placement of Figure 13(a) has smaller thickness for the left contour and can preserve a better standard-cell placement region. A narrow channel, which is formed between two or more macros, usually incurs serious routing congestion [8,11]. Figure 14 shows an example of a narrow channel.…”

“…The work [10] classifies mixed-size placement algorithms into three types: (1) One-stage mixed-size placement: places macros and standard cells simultaneously; for example, ComPLx [16], FastPlace3.0 [19], Hsu et al [10,11], MAPLE [17], mPL [4], NTUplace3 [6], and SimPL [15]. A significant challenge of this approach lies in the legalization and orientation of large macros, which often make the placers of this type generate non-legalized placements.…”

“…As a result, routability plays an essential role for modern circuit placement, and thus recent placement contests (hosted by IBM Research) are focused on routability-driven placement; for example, DAC 2012 [1] and ICCAD 2012 [2] placement contests. For routabilitydriven macro placement, macro porosity [12,14] and narrow channel [8,11] are two dominating effects that deteriorate placement routability, where the macro porosity effect is referred to as the routing resource unavailability in the metal layers above a macro, and the narrow channel effect as the routing congestion occurred between two or more adjacent macros. Nevertheless, existing wirelength models cannot accurately capture these effects for routability control.…”

Closing the Gap between Global and Detailed Placement

“…In [3], a net based removal algorithm is proposed to reduce congestion. The work done in [5,4] directly models routing overflow penalty in the nonlinear optimization. In [20], the placer adopted from the SimPL framework [9] expands look ahead region with precise amount of white space to meet routing demand.…”