This study presents the design and implementation of a 6.78 MHz wireless power transfer (WPT) system that uses magnetically coupled resonance for 5 W mobile phone charger applications. For a resonant WPT system, one of the most significant design issues is the power receiver because of its resonant characteristics. A compact resonant-type power receiver is required for high efficiency and robustness. To realise a compact size, a fully integrated 5 W power receiver that includes an on-chip AC-DC converter and a DC-DC converter is implemented. A protection circuit that operates only during initial power-up is proposed to protect the power switches in the receiver. The proposed receiver was implemented using a 0.18 µm bipolarcomplementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor process with a die area of 3.5 mm × 3.5 mm. The measured maximum power transfer efficiency of the receiver and peak efficiency of the system was 81 and 51%, respectively.

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .

We present a novel nonlinear microfluidic cell stretching (μ-cell stretcher) platform that leverages viscoelastic fluids, i.e., methylcellulose (MC) solutions, and cell mechanoporation for highly efficient and robust intracellular mRNA delivery.

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are e®ectively achieved by employing both a row-column structure and a (CSA) structure as the°oor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-m CMOS process with an active area of 2.445 mm 2 , which achieves a di®erential non linearity (DNL) of 0.25 LSB and an integral nonlinearity (INL) of 0.19 LSB. Additionally, the SFDR increases by 13.2 dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176 mW from a 1.8-V supply voltage.

The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

A rail-to-rail (R-to-R) regulating voltage-controlled oscillator (VCO) is employed to generate multiple-phase clocks for clock and data recovery in a display driver IC (DDI). To achieve a low supply and ground noise sensitivity, the proposed R-to-R regulating method generates VSP and VSN as the supply and the ground of the VCO instead of VDD and VSS. By applying the proposed method, the frequency-VDD variation rate of the VCO (%−f VCO / %−VDD) changes from 3.5%−f VCO /1%−VDD to 0.0073%−f VCO / 1%−VDD within the V ctrl range of 0.5-1.2 V. The DDI is fabricated in a 1P6M 0.18 μm 1.8 V CMOS technology for the interface block and in a 1.6 μm 18 V CMOS technology for the DAC. The R-to-R regulating VCO has a tuning range of 140-240 MHz with linear and small gain (K VCO) characteristics, and is suitable for the phaselocked loop used in flat-panel display interfaces that operate from 0.3 to 2 Gbits/s.