A voltage-current (V-I) converter-based voltage-controlled oscillator (VCO) is adapted to generate multiple-phase clocks for clock and data recovery for a display driver IC. The proposed V-I converter changed the second-order current equation of the VCO to a first-order current equation of the VCO, to achieve a wide operating frequency range, a linear gain (K VCO ) within a wide control voltage, low power, and a small area without any extra circuits, such as a low-to-full amplifier. Owing to the V-I converter, K VCO is changed from 8.43 to 2.05 MHz/mV with a wider V ctrl range, and its tuning range is changed from 114 to 452 MHz with a linear gain characteristic. The proposed VCO is implemented in a 1P6M 1.8 V technology and is suitable for the phase-locked loop used in flat-panel display interfaces that operate from 0.3 to 2 Gbit/s. Introduction: Recent trends in the flat-panel display industry demand both high resolution and cost reduction, which require higher data rates and minimum PCB lines. This can be achieved by using a pair of high-frequency clock-embedded signals (CESs) for data transmission between the timing controller and the display driver IC (DDI). In a clock-embedded interface, the voltage-controlled ring-oscillator-based phase-locked loop (PLL) can be used to generate multiple-phase clocks for clock and data recovery (CDR) [1].Since a display application can be operated at various frame rates ranging from 60 to 240 Hz, the ratio of maximum-to-minimum operating frequency should be large. To stabilise the loop characteristics of a PLL that operates within such a wide-frequency range, the voltagecontrolled ring oscillator needs to be designed to achieve the following characteristics: wide operating frequency range, linear gain (K VCO ) for a wide control voltage (V ctrl ) range, low power, small area, and supply noise immunity [2]. The linear gain can be achieved by regulating the supply voltage of the voltage-controlled oscillator (VCO) to match V ctrl . Thus, the frequency of the VCO is controlled by the supply voltage of the VCO [2, 3].When adjusting the frequency by regulating the supply power, the amplitudes of output signals generated by the VCO can be low at the operating frequency. Therefore, the VCO output cannot be used directly in the phase detector because of its low-voltage level. To solve this problem, the low-to-full (L-F) amplifier is applied to the VCO output to regain the full supply voltage level [2,3]. To achieve CDR in a display application, the L-F amplifier must be applied to all multiplephase clocks generated by the VCO. As a result, the area and current consumption increase because of the extra circuits. Owing to this drawback, the supply-power-regulated VCO is not suitable for a PLL in a display application.To avoid the above-mentioned problems, the works in [4-6] used a ring VCO that maintains a full supply voltage swing without regulating the VCO power. One study proposed an approach to reduce the supply noise sensitivity but failed to secure a linear VCO gain [4]. Other ...
A rail-to-rail (R-to-R) regulating voltage-controlled oscillator (VCO) is employed to generate multiple-phase clocks for clock and data recovery in a display driver IC (DDI). To achieve a low supply and ground noise sensitivity, the proposed R-to-R regulating method generates VSP and VSN as the supply and the ground of the VCO instead of VDD and VSS. By applying the proposed method, the frequency-VDD variation rate of the VCO (%−f VCO / %−VDD) changes from 3.5%−f VCO /1%−VDD to 0.0073%−f VCO / 1%−VDD within the V ctrl range of 0.5-1.2 V. The DDI is fabricated in a 1P6M 0.18 μm 1.8 V CMOS technology for the interface block and in a 1.6 μm 18 V CMOS technology for the DAC. The R-to-R regulating VCO has a tuning range of 140-240 MHz with linear and small gain (K VCO) characteristics, and is suitable for the phaselocked loop used in flat-panel display interfaces that operate from 0.3 to 2 Gbits/s.
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