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This study presents the design and implementation of a 6.78 MHz wireless power transfer (WPT) system that uses magnetically coupled resonance for 5 W mobile phone charger applications. For a resonant WPT system, one of the most significant design issues is the power receiver because of its resonant characteristics. A compact resonant-type power receiver is required for high efficiency and robustness. To realise a compact size, a fully integrated 5 W power receiver that includes an on-chip AC-DC converter and a DC-DC converter is implemented. A protection circuit that operates only during initial power-up is proposed to protect the power switches in the receiver. The proposed receiver was implemented using a 0.18 µm bipolarcomplementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor process with a die area of 3.5 mm × 3.5 mm. The measured maximum power transfer efficiency of the receiver and peak efficiency of the system was 81 and 51%, respectively.

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are e®ectively achieved by employing both a row-column structure and a (CSA) structure as the°oor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-m CMOS process with an active area of 2.445 mm 2 , which achieves a di®erential non linearity (DNL) of 0.25 LSB and an integral nonlinearity (INL) of 0.19 LSB. Additionally, the SFDR increases by 13.2 dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176 mW from a 1.8-V supply voltage.

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This paper presents a capacitor-less low-dropout (LDO) regulator for on-chip mobile applications. An additional push-pull current with a capacitive coupling circuit is proposed to significantly enhance the transient response of the LDO regulator. The proposed LDO regulator can deliver an output current of 100 mA with a minimum dropout voltage of 0.4 V. The circuit was modeled and implemented in a 0.35-µm CMOS process with a die area of 0.22 mm 2 . The experimental results show that the LDO regulator can be recovered within 0.5 µs at a voltage spike less than 90 mV.