Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the "Internet of Things" (IoT). IoT is now part of our life and we have to deal with it. More than 10 billion devices are already connected and five times more are expected to be deployed in the next five years. While deployment and integration of IoT is expanding, one of the main challenge is to provide practical solutions to security, privacy and trust issues in IoT. Protection and security mechanisms need to include features such as interoperability and scalability but also traceability, authentication and access control while remaining lightweight. Among the most promising approaches to such security mechanisms, physical unclonable functions (PUF) provide a unique identifier for similar but different integrated circuits using some of their physical characteristics. These types of functions can thus be used to authenticate integrated circuits, provide traceability and access control. This paper presents a comprehensive case study of the transient effect ring oscillator (TERO) PUF from its implementation on FPGAs to its complete characterization. The implementation of the PUF is detailed for two different families of FPGAs: Xilinx Spartan 6 and Altera Cyclone V. All the metrics used for the characterization are explained in detail and the results of the characterization include robustness to environmental parameters including variations in temperature and voltage. Finally, we compare our results with those obtained for another PUF: the ring oscillator (RO) PUF. All the design files are available online to ensure repeatability and enable comparison of our contribution with other studies.

Teaching FPGA security to electrical engineering students is new at graduate level. It requires a wide field of knowledge and a lot of time. This paper describes a compact course on FPGA security that is available to electrical engineering master's students at the Saint-Etienne Institute of Telecom, University of Lyon, France. It is intended for instructors who wish to design a new course on this topic. The paper reviews the motivation for the course, the pedagogical issues involved, the curriculum, the lab materials and tools used, and the results. Details are provided on two original lab sessions, in particular, a compact lab that requires students to perform differential power analysis of FPGA implementation of the AES symmetric cipher. The paper gives numerous relevant references to allow the reader to prepare a similar curriculum.

As the complexity of System-on-Chip (SoC) and the reuse of third party IP continues to grow, the security of a heterogeneous SoC has become a critical issue. In order to increase the software security of such SoC, the TrustZone technology has been proposed by ARM to enforce software security. Nevertheless, many SoC embed non-trusted third party Intellectual Property (IP) trying to take the benefits of this technology. In such case, is the security guaranteed by the ARM TrustZone technology reduced by the heterogeneity of SoC? In order to answer to this question, this paper presents relevant attack scenarios based on third party IP to exploit some security failures of the TrustZone extension through the all SoC. At the end, this article proposes to SoC designers to consider some design solutions to limit the impact of a malicious IP.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Emerging non-volatile memories are getting new interest in the system design community. They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures. Hafnium oxide-based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic-in-memory designs. Indeed, this compatibility leads to various possibilities for fine-grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system. Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology.In this article, we focus on ferroelectric field-effect transistors (FeFET) and present an overview of three different fine-grain logic-in-memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address. All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.

The increasing production costs of electronic devices and changes in the design methods of integrated circuits (ICs) has led to emerging threats in the microelectronics industry. Today, high value chips are the target of counterfeiting, theft and malicious hardware insertion (such as hardware trojans). Intellectual property (IP) protection has become a major concern and we propose to fight counterfeiting and theft by designing salutary hardware (salware). Instead of insert malicious effects inside an IP like a malware (e.g. a hardware trojan), a salware uses the same techniques, strategies and means for IP protection. One of the most studied salware is IP watermarking. Many works propose to target the finite state machine of digital IP to perform the watermarking. But, most of the time, the verification of the watermark is not clearly described. This conduces to a lack of credibility of these works. This paper proposes a watermark verification scheme using a correlation analysis based on the measurement of the IC power consumption. This article presents this process of verification and also discusses the selection of its parameters according to experimental results.

International audienceOver the past 10 years, the multitude of highly constrained applications such as radio-frequency identification and sensor networks has led to a new trend in the development of cryptographic primitives. Many algorithms categorized as lightweight cryptographic algorithms have been developed specifically for these new applications. Comparing them is very important but also very challenging because every application has its own constraints. This fact leads to a different choice of design strategies, and the best algorithm for one application is not necessarily the best for all applications. Moreover, the definition of what is lightweight is not always the same because lightweight covers a reduction in power and energy consumption just as well as a reduction in area for hardware. This article proposes and compares lightweight hardware implementations of four recent block ciphers (Klein, Led, Lilliput, and Ktantan). This work is included in a large project that aims to protect the hardware against cloning and counterfeiting. The main constraint in this field is the area required by the protection scheme. As a result, we chose to target only the smallest possible area for each selected algorithm. Consequently, two strategies are presented: full width and serial hardware implementations. All results were generated and verified for Xilinx Spartan-6 and Spartan-3 field-programmable gate arrays and also for application-specific integrated circuit. Additionally, all the design files are available online

Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.