Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes

Marchand, Cédric; Bossuet, Lilian; Gaj, Kris

doi:10.1002/cta.2288

Cited by 9 publications

(9 citation statements)

References 21 publications

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“…Another important point is realizing the implementations on a different FPGA platform, for example, Xilinx, or different FPGA families from the same platform. In fact, the benefit of such exercise is limited because the relative performance of the implementations is almost the same across platforms, as demonstrated in the research work of Mohd et al 50 which compared Xilinx and Altera implementations and in the research work of Marchand et al 54 which compared implementation results of two Xinlinx FPGA families.…”

Section: Methodsmentioning

confidence: 99%

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Abed

Mohd

Hayajneh

et al. 2021

Circuit Theory & Apps

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Summary Hardware Trojans (HTs) are malicious and intentional modification of the hardware design, embedded by an adversary to leak sensitive data, modify functionality, or cause malfunction. Lightweight ciphers are designed for resource‐constrained devices (RCDs) to balance resources and security, but often targeted by HTs. This work aims to create a trusted lightweight cipher design and detect complex sequential HTs using a runtime monitoring method with minimal resource overhead. The novelty of the approach is that it combines full or partial temporal redundancy, resource minimization, and runtime monitoring. The algorithm employs temporal redundancy, by executing a first run of the cipher, and then replays the cipher fully (ReplayN method) or partially (ReplayN/2 method). A mismatch indicates HT activity, and a third replay is executed to determine the correct results. The ReplayN/2 algorithm further optimizes time and energy by limiting replay to the second half of the cipher rounds. The proposed method is compared with other existing methods including triple modular redundancy (TMR), adapted triple modular redundancy (ATMR), and reverse‐function redundancy (RFR). All methods were implemented in field‐programmable gate array (FPGA) technology. Implementation performance metrics were measured and compared, including resource utilization (i.e., logical elements [LEs]), power, energy (E), and speed (i.e., Fmax). The results show that the proposed algorithm outperforms existing methods in most of the metrics. In terms of speed and area, the replay algorithm is faster by 24% and reduces total LEs by 42% when compared with existing methods. Regarding power, replay algorithm reduces power by 45% when compared with TMR and ATMR. With respect to energy, replay methods reduce energy by an average of 6% when compared with TMR and ATMR. The ReplayN/2 reduces energy by an average 15% when compared with TMR and ATMR. Based on the normalE×LE (i.e., energy × area) metric, ReplayN/2 is the top performing method as it balances area and energy metrics. Using normalE×LEnormalFmax metric, the replay methods are the best performing methods as they best balance area, energy, and speed. Also, based on ThroughputLE2 metric, the replay methods are the top performing methods.

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Section: Methodsmentioning

confidence: 99%

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Abed

Mohd

Hayajneh

et al. 2021

Circuit Theory & Apps

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“…Marchand et al [21] provided another interesting hardware implementation of block ciphers (Klein, Led, Lilliput, and Ktantan). Hardware implementations for these block ciphers follow two strategies: full-width and serial.…”

Section: Related Workmentioning

confidence: 99%

“…The implementation of block ciphers is listed next [21]. All the block ciphers consume fewer hardware resources compared to the Gimli implementation.…”

Section: Comparisonmentioning

confidence: 99%

A Flexible Gimli Hardware Implementation in FPGA and Its Application to RFID Authentication Protocols

2021

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Radio Frequency Identification (RFID) systems have bestowed numerous conveniences in a multitude of applications, but the underlying wireless communications architecture makes it vulnerable to several security threats. To mitigate these issues, various authentication protocols have been proposed. The literature accommodates comprehensive proposals and analysis of authentication protocols, but not many of them provide hardware implementations. In addition, there is diverse demand for hardware area and throughput (TP) requirements from RFID system components (tags, readers, database servers), which demand a flexible implementation strategy. This paper proposes a flexible implementation strategy for the lightweight authenticated encryption (AE) and hash function called Gimli, and applies it to a state-of-theart authentication protocol. This allows the authentication protocol to be implemented efficiently, wherein the area and TP can be adjusted flexibly according to the RFID system requirements. This implementation strategy is generic; it can be used to implement any other AE and hash functions. This strategy can also be applied to other authentication protocols that heavily use AE and hash functions. To provide a detailed analysis, the hardware are optimization techniques in each component of the RFID system for a state-ofthe-art authentication protocol are analyzed. When implemented with the most area-optimized versions, we achieve TP of 740 Mbps and 420 Mbps for Gimli hash and Gimli AE, respectively, and for throughputoriented implementation, the results are 3.08 Gbps and 1.43 Gbps, respectively. This shows that the proposed implementation strategies allow us to implement authentication protocols in a flexible manner to meet the differing requirements in TP and area for RFID applications.

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“…In [22][23][24], the authors use only generic components such as FFs, LUTs, maximum frequency, and throughput. In fact, other design parameters, a trade-off between area and throughput representing the efficiency, and power consumption have to be considered.…”

Section: Hardware Implementationmentioning

confidence: 99%

Hardware Implementation of Secure Lightweight Cryptographic Designs for IoT Applications

Youssef

Abdelli

Dridi

et al. 2020

Security and Communication Networks

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The recent expansion of the Internet of Things is creating a new world of smart devices in which security implications are very significant. Besides the claimed security level, the IoT devices are usually featured with constrained resources, such as low computation capability, low memory, and limited battery. Lightweight cryptographic primitives are proposed in the context of IoT while considering the trade-off between security guarantee and good performance. In this paper, we present optimized hardware, lightweight cryptographic designs, of 32-bit datapath, LED 64/128, SIMON 64/128, and SIMECK 64/128 algorithms, for constrained devices. Our proposed designs are investigated on Spartan-3, Spartan-6, and Zynq-7000 FPGA platforms in terms of area, speed, efficiency, and power consumption. The proposed designs achieved a high throughput up to 891.99 Mbps, 838.95 Mbps, and 210.13 Mbps for SIMECK 64/128, SIMON 64/128, and LED 64/128 on Zynq-7000, respectively. A deep comparison between our three proposed designs is elaborated on different FPGA families for adequate FPGAs-based application deployment. Test results and security analysis show that not only can our proposed designs achieve good encryption results with high performance and a low reduced cost but also they are secure enough to resist statistical attacks.

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Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes

Cited by 9 publications

References 21 publications

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

A Flexible Gimli Hardware Implementation in FPGA and Its Application to RFID Authentication Protocols

Hardware Implementation of Secure Lightweight Cryptographic Designs for IoT Applications

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