I. AbstractA high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (V dd =1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 µm 2 . II. Technology DescriptionThe major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated. III. FEOL Performance ResultsA plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-cur...
I. AbstractA high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2x wiring levels, and increased 1x wire aspect ratios in lowk, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK Chip-Package Interaction (CPI) reliability, including in the most aggressive organic flipchip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria. II. BEOL IntegrationAggressive 0.7x scaling from 65nm BEOL wiring and contact dimensions has been achieved using hyper-NA (1.2NA) lithography. This enables a 2x active area reduction for migratable designs. The 45 nm BEOL hierarchy is shown in Fig. 1. At the 1x wiring levels (M1-M3), BEOL delays are largely impacted by resistance increases from scaling. Increased aspect ratio in conjunction with an optimized Cu barrier-seed process results in up to 25% resistance and 20% RC reductions, respectively, per Fig. 2. Typically, increasing Cu aspect ratios degrades stress migration (SM) and electromigration (EM) reliability. However, Figs. 3-4 show than an optimized Cu barrier-seed process and tooling enables zero SM fails and good EM performance. Thus scaling impacts to BEOL parasitics at 45 nm 1x levels are mitigated, while extending the low-k SiCOH film and integration scheme [1] from 90 and 65 nm technologies [2]. The industry-wide effort to integrate ULK BEOL dielectrics has focused primarily on the 1x wiring levels [3][4][5]. In contrast, our strategy is to introduce ULK at the 2x levels (M4-M6), which are typically dominated by relatively longer RC-dominated runs. The 15% RC benefit for ULK (k=2.4) over low-k (k=3.0) at these levels, as shown in Fig. 5, is leveraged to deliver superior BEOL performance at reduced risk. These 2x levels consist of dual damascene Cu in homogeneous PECVD ULK porous-SiCOH which is based on advanced precursors and UV-cure tooling [6][7]
The microstructure of Cu interconnects fabricated with Ta and Co liner materials had been examined by transmission electron microscopy and correlated to the electrical characteristics. Cu lines of 40 nm width were fabricated on 300 mm Si wafers by conventional CMOS backend processing. Electrical measurements performed immediately after fabrication of these Cu lines showed similar electrical resistance for Co and Ta liners. However, a 2.5-hour anneal at 375°C led to 5% more resistance reduction for Cu lines with the Ta liner than with the Co liner. Microstructure analyses showed that Cu lines with the Ta liner had 24% coherent Σ3 grain boundaries while lines with the Co liner yielded only 6% of coherent grain boundaries. In addition, Cu with Ta liner had a stronger 〈111〉 texture along the line width direction. However, the overall grain size distribution was similar between Ta and Co liners. These results suggest Co liner has some impact on Cu microstructures, which may be a root cause for the relatively higher line resistance.
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