Spatial atomic layer deposition (SALD) is gaining traction in the thin film electronics field because of its ability to produce quality films at a fraction of the time typically associated with ALD processes. Here, we explore the process space for the fabrication of thin film patterned-by-printing electronics using the combination of SALD and selective area patterning. First, a study of SALD growth conditions for the three primary components of our metal oxide thin film electronics, namely alumina (Al2O3) dielectric, zinc oxide (ZnO) semiconductor, and aluminum doped ZnO (AZO) conductor, provides insight into the potential trade-offs in performance, substrate latitude (temperature), and process speed. At constant precursor partial pressures, the precursor exposure times and substrate temperatures were varied from 25 to 400 ms and from 100 to 300 °C, respectively. The very short gas exposure and purge times obtainable only with a spatial implementation of ALD are shown always to be advantageous for throughput and process speed, even though growth is far from the “ideal” ALD condition of saturated monolayer growth. Using the same range of process conditions, we evaluated the ability of very thin layers of poly(vinyl pyrrolidone) (PVP) to inhibit film growth. We demonstrate that PVP sufficiently inhibits the growth of all three materials at temperatures at or above 150 °C to usefully pattern high-quality electronic devices. Additionally, we found that very thin layers of PVP are most effective at higher temperatures and fast ALD cycles. Thus, faster SALD cycles are advantageous from both throughput and patterning performance perspectives.

We demonstrate thin-film transistors with the fabrication advantages associated with printed electronics and the device performance associated with inorganic materials that are typically patterned via photolithography. In this process a polymeric material is printed to selectively inhibit the deposition of the electrically active material, which is globally applied via spatial atomic layer deposition. We identify water-soluble inhibitors that make attractive choices for printable ink formulations and explore the interactions of two examples of polymeric inhibitors with the process space. Using this knowledge we demonstrate zinc oxide thin film transistors, patterned entirely by inkjet-printed polyvinyl pyrrolidone.

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.