Multilocus genome-wide association studies (GWAS) have become the state-of-the-art procedure to identify quantitative trait nucleotides (QTNs) associated with complex traits. However, implementation of multilocus model in GWAS is still difficult. In this study, we integrated least angle regression with empirical Bayes to perform multilocus GWAS under polygenic background control. We used an algorithm of model transformation that whitened the covariance matrix of the polygenic matrix K and environmental noise. Markers on one chromosome were included simultaneously in a multilocus model and least angle regression was used to select the most potentially associated single-nucleotide polymorphisms (SNPs), whereas the markers on the other chromosomes were used to calculate kinship matrix as polygenic background control. The selected SNPs in multilocus model were further detected for their association with the trait by empirical Bayes and likelihood ratio test. We herein refer to this method as the pLARmEB (polygenic-background-control-based least angle regression plus empirical Bayes). Results from simulation studies showed that pLARmEB was more powerful in QTN detection and more accurate in QTN effect estimation, had less false positive rate and required less computing time than Bayesian hierarchical generalized linear model, efficient mixed model association (EMMA) and least angle regression plus empirical Bayes. pLARmEB, multilocus random-SNP-effect mixed linear model and fast multilocus random-SNP-effect EMMA methods had almost equal power of QTN detection in simulation experiments. However, only pLARmEB identified 48 previously reported genes for 7 flowering time-related traits in Arabidopsis thaliana.

No abstract

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.

No abstract

No abstract

No abstract

No abstract

High performance low-dropout regulators (LDOs) are indispensable in a systemon-a-chip (SoC) due to their low output noise, fast transient response and good power supply rejection (PSR) characteristics. In general, differential analog circuit loads need an LDO with high PSR, digital circuit loads need an LDO with fast load transient response, while single-ended analog/RF circuit loads need an LDO with both high PSR and fast transient response. Figure 17.11.1 shows an LDO embedded in an optical receiver that helps improve the sensitivity of the front-end system. On-chip LDOs with PSR in the GHz range are in high demand for wideband optical communication systems because there is only one photo detector in the optical receiver and supply voltage variations would degrade its sensitivity severely [1].Off-chip capacitors are conventionally connected to supplies for filtering purposes. With a large output capacitor C L , say 1μF, small ripples due to load transients and good PSR can be achieved [2]. However, for a fully-integrated LDO, large C L is no longer available, so both transient responses and PSR performance will degrade significantly. Many fully-integrated LDOs with limited on-chip capacitance (a.k.a. capacitor-less LDOs) have been proposed in the past decade [3]- [6]. A figure-of-merit (FOM) of LDOs, shown in Fig. 17.11.1, is defined in [3], where I Q is the quiescent current, and the response time, T R , is a function of on-chip capacitance, C, load-transient of output voltage, ΔV OUT , and maximum load, I MAX . A considerably large current (6%) was used in [3] to move the non-dominant poles to high frequencies. A single-transistor-control LDO based on the flipped voltage follower (FVF) topology provided stable regulation at various C L conditions including the capacitor-less case in [4], but it was sensitive to PVT variations, and was not fast enough with undershoots of 160mV observed. The FVF was also employed in [5] with a slew-rate enhancement circuit that responded to load-transient edges of 100ns. However, its PSR degraded to 0dB before reaching 1MHz. An ultra-fast-response comparatorbased regulator in 45nm SOI process was proposed in [6] that consumed 12mA of I Q and required a deep-trench capacitor of 1.46nF, and its intrinsic 10mV ripple was not suitable for RF/analog front-end circuits.For an LDO, the largest capacitors are the output capacitor C L and the power MOS gate capacitor C G . Hence, there are at least two low-frequency (LF) poles: the output pole, p OUT , and the pole at the gate of the power MOS, p G . The pole p OUT would shift to a lower frequency when R L increases and vice versa. Basically, LDOs with an off-chip C L are designed to be p OUT dominant [2], while all previous fully-integrated analog LDOs have an internal dominant pole [3]- [5]. Therefore, LDOs can be classified by the need for an off-chip C L , or by being output-pole dominant or internal-pole dominant. Thus, there are 4 combinations for which the pros and cons are summarized in the table of Fig. 17.11.1. An output-pole ...