Near speed-of-light signaling over on-chip electrical interconnects

Rs, Chang; Talwalkar, N.; Yue, C. Patrick; Wong, S.S.

doi:10.1109/jssc.2003.810060

Cited by 112 publications

(75 citation statements)

References 10 publications

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“…Circuit-level studies (e.g., [16], [17], [21], [34]) have been carried out to characterize the performance of transmission line based onchip interconnect. Novel signaling and modulation schemes have been proposed [14], [25].…”

Section: Background and Related Workmentioning

confidence: 99%

A design space exploration of transmission-line links for on-chip interconnect

Carpenter¹,

Hu$^{²,

Huang³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient. Well-engineered transmission linebased communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level analyses and tradeoffs. This paper makes a first-step effort in exploring part of the design space. Using detailed simulation-based analysis, we show that a shared-medium fabric based on transmission line can offer better performance and a much better energy profile than a conventional mesh interconnect.

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Section: Background and Related Workmentioning

confidence: 99%

A design space exploration of transmission-line links for on-chip interconnect

Carpenter¹,

Hu$^{²,

Huang³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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show abstract

“…In [6], interconnects consist of wires with varying latency, bandwidth, and energy characteristics, and are mapped on appropriate interconnects for cache coherence operations. In [5], transmission line technology [4] is exploited to access level-2 on-chip caches. Our SKB study was partially stimulated by the results in [4,5].…”

Section: Related Workmentioning

confidence: 99%

“…In [5], transmission line technology [4] is exploited to access level-2 on-chip caches. Our SKB study was partially stimulated by the results in [4,5].…”

Section: Related Workmentioning

confidence: 99%

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The SKB: A Semi-Completely-Connected Bus for On-Chip Systems

Takesue

2007

Lecture Notes in Computer Science

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Abstract. This paper proposes a semi-completely-connected bus, called SKB, to alleviate the long-wire and pin-neck problems against on-chip systems through a small diameter and dynamic clustering. Dynamic clustering allows to reduce the traffic to the per-cluster units such as the global interconnect interface, as compared with the static clustering fixed in hardware. We derive a 2 n -node semi-complete (SK) graph from a simple node-partitioning. An SKB is produced from the SK graph when we replace the links incident to a node by a single bus for the node. The diameter of SKB equals 1 (bus step), though the bus length is rather long, O( √ 2 n ). Simulation results show that relative to the hypercube with the link delay of 1 clock, the SKB's bandwidth is about 0.97 and 0.14 assuming the bus delay of 1 and 8 clocks, respectively, that increases to about 4.57 and 0.71 with the dynamic clustering.

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“…Among these solutions, repeater insertion is simple, but the performance is limited by the area and delay from the inserted cell itself [2]. Modulation [3] and transmission line [4] benefit from the effect of the wire inductance, however, they tend to operate at very high frequency or need larger sized wires. Current mode signaling can achieve high speed, but has problems from power consumption [5].…”

Section: Introductionmentioning

confidence: 99%

Design optimization for capacitive-resistively driven on-chip global interconnect

Jiang

et al. 2015

IEICE Electron. Express

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On-chip global wires are speed and power bottleneck in state-ofthe-art chips. AC coupling technique is an efficient way to reduce interconnection delay and power. This paper proposes a new capacitive-resistively driven AC coupling global link. Bandwidth performance of the proposed wire is analyzed and an optimization algorithm for capacitiveresistively driven wire is presented. Simulation results show that our optimization methodology can improve the bandwidth. By applying our optimization algorithm, data rate can be improved from 2 Gb/s to 2.5 Gb/s in the implemented transceiver circuit. The proposed optimization algorithm can be applied in high speed global communication.

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Near speed-of-light signaling over on-chip electrical interconnects

Cited by 112 publications

References 10 publications

A design space exploration of transmission-line links for on-chip interconnect

A design space exploration of transmission-line links for on-chip interconnect

The SKB: A Semi-Completely-Connected Bus for On-Chip Systems

Design optimization for capacitive-resistively driven on-chip global interconnect

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