No abstract

Deformation of interconnect structures at the back-end of microelectronic devices during processing or service can have a pronounced effect on component reliability. Here, we use atomic force microscopy (AFM) to study plastic deformation and interfacial sliding of Cu interconnects on Si. The behavior of both standalone Cu lines and lines embedded in a low-K dielectric (LKD) was studied. Following thermal cycling, changes were observed in the in-plane (IP) Cu line dimensions, as well as the out-of-plane (OOP) step height between Cu and the dielectric in single-layer structures. These were attributed to differential deformation of the Cu/Si and Cu/dielectric material pairs caused by thermal expansion mismatch, accommodated by interfacial creep. These results are discussed in light of previous work on the mechanism of interfacial creep. A simple shear-lag-based model, which may be used to estimate the extent of interfacial sliding, is proposed. Some experimental results on the distortion of Cu lines caused by package-level stresses following thermal cycling are also presented.

No abstract

Interconnect structures at the back-end of microelectronic devices can deform via unusual, scale-sensitive phenomena due to thermo-mechanical loads sustained during processing, or during service as part of a microelectronic package.Although small, these effects can have a pronounced effect on component reliability. Here, we present results of atomic force microscopy (AFM) studies on Cu-low K dielectric (LKD) hack-end interconnect structnres (BEIS) to demonstrate these effects, which include creep/plasticity of interconnect lines, and diffusionally accommodated sliding at Cu-LKD interfaces. These effects may result in in-plane (IF' ) changes in Cu line dimensions, cause strain incompatibilities between Cu and LKD in the out-of-plane (OOP) direction, and cause Cu lines to migrate or crawl under far-field shear stresses imposed by the package. A shear-lag based model is utilized to simulate OOP deformation in a Cu-LKD single layer BEIS under thermal cycling conditions associated with back-end processing. A separate model, which simulates I F ' deformation of Cu interconnects embedded in LKD under -' The maximum t-raturc of 723K -ms the processing temperature of the L K D The device is exposed to rcvnal cycles up to this tcmprratlm as multiple M K D layare dcporitcd on the chip during production of a multi-layer BEIS.