Modeling of interfacial sliding and film crawling in back-end structures of microelectronic devices

Abstract

Interconnect structures at the back-end of microelectronic devices can deform via unusual, scale-sensitive phenomena due to thermo-mechanical loads sustained during processing, or during service as part of a microelectronic package.Although small, these effects can have a pronounced effect on component reliability. Here, we present results of atomic force microscopy (AFM) studies on Cu-low K dielectric (LKD) hack-end interconnect structnres (BEIS) to demonstrate these effects, which include creep/plasticity of interconnect lines, and diffusionally accommodated sliding at Cu-LKD interfaces. These effects may result in in-plane (IF' ) changes in Cu line dimensions, cause strain incompatibilities between Cu and LKD in the out-of-plane (OOP) direction, and cause Cu lines to migrate or crawl under far-field shear stresses imposed by the package. A shear-lag based model is utilized to simulate OOP deformation in a Cu-LKD single layer BEIS under thermal cycling conditions associated with back-end processing. A separate model, which simulates I F ' deformation of Cu interconnects embedded in LKD under -' The maximum t-raturc of 723K -ms the processing temperature of the L K D The device is exposed to rcvnal cycles up to this tcmprratlm as multiple M K D layare dcporitcd on the chip during production of a multi-layer BEIS.

Wire bond challenges in low‐k devices

“…,30 to 60 ppm/8C), a much larger thermal expansion (a) exists when compared to the Cu layer (17 ppm/8C). Since, the strain is equal to the product of CTE difference and the temperature difference of the bond temperature compared to room temperature, [1 < (a low-k 2 a Cu )(T bond 2 T RT )], increase in a low-k leads to increase in overall thermal stress in the Cu metal lines that can be expressed as follows (Dutta et al, 2004):…”