Issues of submicron integration in vertical topography, junction silicide, and contact integrity are summarid in Fig.1. Examples include (1) high cost of twin-tub formation to achieve planarity at tub boundaries, (2) silicide-related nonuniformity or defects on shallow junctions, and (3) coverage of a TiN diffusion barrier layer at bottom comers of contact windows. We present a simple process to attack the issues. The process requires only ten masks for a full-CMOS integration with two-level metallization. It also improves the integration density and circuit performance.
A cost-effective 0.5 pm lithographic capability has been developed using a reduction stepper with a 0.45 NA I-line lens and new photoresists. Resist proceyses provide excellent CD and sidewall angle control, with satisfactory exposure latitude. Resist pattern fidelity has been improved through computer-optimized reticle pattern modifications using serifs. Focus latitude has been significantly improved by application of new latent image metrology techniques. This paper provides an overview of these of other aspects of the lithographic process.
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