Multiwavelength room temperature photoluminescence (RTPL) and Raman spectroscopy were proposed as in-line monitoring techniques for characterizing the dielectric/Si interface. As an application example, ∼7.0 nm thick ultra-thin SiO 2 films on 300 mm Si wafers, prepared by various oxidation techniques and conditions, were characterized using multiwavelength RTPL and Raman spectroscopy. Specifically, overall quality of the ultra-thin SiO 2 /Si interface (including passivation characteristics) and Si lattice stress beneath SiO 2 films are investigated. The overall SiO 2 /Si interface quality was seen to be very dependent on oxidation technique and process conditions. Within wafer and wafer-to-wafer variations of SiO 2 /Si interface quality were successfully characterized by RTPL and Raman spectra measurements. For electrical analysis of SiO 2 /Si-based structures, non-contact corona charge-based, in-line (capacitance-voltage (C-V) and stress induced leakage current (SILC)) measurements were performed and compared with RTPL and Raman characterization results. Surprisingly, significant variations in RTPL intensity at and near the corona charge-based measurement sites, indicated that the corona-based electrical measurement technique, though non-contact, was indeed invasive. The effect of corona-charge based electrical measurements on SiO 2 /Si interface was permanent and even clearly visible from the back side of the wafer. RTPL intensity variations at and near the measurement sites remained, even after a forming gas anneal. As devices scale to smaller size and complexity of device structures increase, the importance of proper understanding and control of the dielectric/Si interface is increasing. Advanced metal-oxidesemiconductor (MOS) and metal-insulator-semiconductor (MIS) devices employ ultra thin dielectric gate layers. The physical dimensions are in the range of single digit to double digit nanometers. The effective oxide thickness (EOT) is significantly less than 10 nm. Pure SiO 2 or combinations of SiO 2 and SiN layers are typically used as gate dielectrics. Materials with high dielectric constant (high-k dielectrics) and metal gates are also frequently used, depending on chip design.Conventional interface characterization techniques, such as high resolution cross-sectional transmission electron microscopy (HRX-TEM), Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy (XPS) and noncontact electrical measurement tools (for example, I-V, C-V and carrier life-time measurements) are either destructive or invasive (including methods which are non-contact, but impact dielectric/Si interface quality).1-3 The purpose of all these characterization techniques is to gain useful insights into dielectric/Si in various dimensions or aspects. While the conventional characterization techniques provide very useful information on many properties of the dielectric/Si interface, they appear unable to provide additional clues to some puzzling dielectric/Si interface problems....
In this paper, we demonstrated the plasticity mechanism for copper (Cu) extrusion in through-silicon via structures under thermal cycling. The local plasticity was directly observed by synchrotron x-ray micro-diffraction near the top of the via with the amount increasing with the peak temperature. The Cu extrusion was confirmed by Atomic Force Microscopy (AFM) measurements and found to be consistent with the observed Cu plasticity behavior. A simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface. The model predictions were able to account for the via extrusions observed in two types of experiments, with one representing a nearly free sliding interface and the other a strongly bonded interface. Interestingly, the AFM extrusion profiles seemed to contour with the local grain structures near the top of the via, suggesting that the grain structure not only affects the yield strength of the Cu and thus its plasticity but could also be important in controlling the pop-up behavior and the statistics for a large ensemble of vias.
Room temperature photoluminescence (RTPL) spectroscopy was proposed as an in-line monitoring technique for characterizing the dielectric/Si interface. Specifically, Si lattice stress beneath dielectric films and overall quality of the dielectric/Si interface (including passivation characteristics) are investigated. As an application example, ~7.0 nm thick ultra-thin SiO2 films on 300 mm Si wafers, prepared by various oxidation techniques and conditions, were characterized using multiwavelength RTPL spectroscopy. The overall SiO2/Si interface quality was seen to be very dependent on oxidation technique and process condition. Within wafer and wafer-to-wafer variations of SiO2/Si interface quality were successfully characterized by RTPL spectrum measurement and intensity wafer mapping under different excitation wavelengths.
Room temperature photoluminescence (RTPL) spectroscopy and Raman spectroscopy were examined as in-line monitoring techniques for characterizing the interface characteristics of ultra-thin (∼7.2 nm) stacked dielectric films (SiN/SiO 2 ) on 300 mm Si wafers. To investigate the effect of the stacked dielectric films on electronic properties and lattice stress of Si beneath the films, RTPL and Raman signals were measured under various excitation wavelengths with different probing depths. Changes of interface characteristics (mainly, electronic properties and lattice stress of Si beneath the films) of the stacked dielectric films and the Si wafer were investigated using various specimens prepared by different deposition techniques and conditions. The overall interface characteristics of the SiN/SiO 2 /Si specimens was found to be very dependent on the SiN deposition technique and process conditions. As the stoichiometry of SiN films change from N-rich to Si-rich conditions, the RTPL signal becomes weaker, indicating the change of electronic properties at the SiN/SiO 2 /Si interface. Within-wafer and wafer-to-wafer variations of the SiN/SiO 2 /Si interface characteristics were successfully characterized by RTPL and Raman spectroscopy under various excitation wavelengths.Other characterization results such as film thickness from ellipsometry, film stress from wafer curvature and film composition from Auger electron spectroscopy (AES) were also discussed. Advanced metal-oxide-semiconductor (MOS) and metalinsulator-semiconductor (MIS) devices employ ultra-thin dielectric film(s) as gate dielectrics. The physical dimensions are typically on the order of several nanometers. Pure SiO 2 or combinations of SiN and SiO 2 films are typically used. Both physical thickness and effective oxide thickness (EOT) are less than 10 nm.1-2 High dielectric constant materials (high-k dielectrics) and metal gates are also frequently used. Low dielectric constant materials (low-k dielectrics) are used as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD) with Cu interconnects to reduce RC constants (i.e, RC delay) and improve device operation speed.3 As devices scale to smaller size, the complexity of device structures as well as the number of interfaces in dielectric films increases. Proper understanding, monitoring and control of the dielectric/Si interface become very important.Physical dimensions of ultra-thin dielectric film(s) on Si wafers are typically measured using ellipsometry and occasionally verified by high resolution cross-section transmission electron microscopy (HRXTEM). Conventional interface characterization techniques include chemical characterization and electrical characterization. Chemical properties are typically evaluated using Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS).4-6 Films stress is often monitored in blanket Si wafers by measuring the curvature, and its direction, before and after film deposition and treatment.7-10 The stoic...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.