Ultra-Thin SiO₂/Si Interface Quality In-Line Monitoring Using Multiwavelength Room Temperature Photoluminescence and Raman Spectroscopy

Abstract

Multiwavelength room temperature photoluminescence (RTPL) and Raman spectroscopy were proposed as in-line monitoring techniques for characterizing the dielectric/Si interface. As an application example, ∼7.0 nm thick ultra-thin SiO 2 films on 300 mm Si wafers, prepared by various oxidation techniques and conditions, were characterized using multiwavelength RTPL and Raman spectroscopy. Specifically, overall quality of the ultra-thin SiO 2 /Si interface (including passivation characteristics) and Si lattice stress beneath SiO 2 films are investigated. The overall SiO 2 /Si interface quality was seen to be very dependent on oxidation technique and process conditions. Within wafer and wafer-to-wafer variations of SiO 2 /Si interface quality were successfully characterized by RTPL and Raman spectra measurements. For electrical analysis of SiO 2 /Si-based structures, non-contact corona charge-based, in-line (capacitance-voltage (C-V) and stress induced leakage current (SILC)) measurements were performed and compared with RTPL and Raman characterization results. Surprisingly, significant variations in RTPL intensity at and near the corona charge-based measurement sites, indicated that the corona-based electrical measurement technique, though non-contact, was indeed invasive. The effect of corona-charge based electrical measurements on SiO 2 /Si interface was permanent and even clearly visible from the back side of the wafer. RTPL intensity variations at and near the measurement sites remained, even after a forming gas anneal. As devices scale to smaller size and complexity of device structures increase, the importance of proper understanding and control of the dielectric/Si interface is increasing. Advanced metal-oxidesemiconductor (MOS) and metal-insulator-semiconductor (MIS) devices employ ultra thin dielectric gate layers. The physical dimensions are in the range of single digit to double digit nanometers. The effective oxide thickness (EOT) is significantly less than 10 nm. Pure SiO 2 or combinations of SiO 2 and SiN layers are typically used as gate dielectrics. Materials with high dielectric constant (high-k dielectrics) and metal gates are also frequently used, depending on chip design.Conventional interface characterization techniques, such as high resolution cross-sectional transmission electron microscopy (HRX-TEM), Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy (XPS) and noncontact electrical measurement tools (for example, I-V, C-V and carrier life-time measurements) are either destructive or invasive (including methods which are non-contact, but impact dielectric/Si interface quality).1-3 The purpose of all these characterization techniques is to gain useful insights into dielectric/Si in various dimensions or aspects. While the conventional characterization techniques provide very useful information on many properties of the dielectric/Si interface, they appear unable to provide additional clues to some puzzling dielectric/Si interface problems....

Communication—In-Line Detection of Silicon Surface Quality Variation Using Surface Photovoltage and Room Temperature Photoluminescence Measurements

“…RTPL studies showed very high sensitivity to surface passivation, native oxide/Si interface quality, 6 dielectrics/Si interface quality, 7 plasma induced damage (PID), 8 to 10 12 cm −3 showed good correlation between photoconductance decay (PCD) lifetime, SPV diffusion length (DL) and iron readings. 15 RTPL was reported to be sensitive to iron contamination at concentrations exceeding 10 10 cm −3 (<ppb) as calibrated by SPV using lightly doped p-type silicon.…”

“…RTPL measurements, intensity and spectral distribution from the Si wafers, were mapped in the wavelength range of 900 ∼ 1400 nm under 650 and 827 nm excitation with penetration depths of ∼4.0 and ∼10 μm. 6,7 Both SPV and RTPL mapping was done on five wafers per batch in * Electrochemical Society Member.…”

“…In this study, the root cause of a recent incident generating a large number of particle/defects was investigated using surface photovoltage (SPV) 5 and multiwavelength room temperature photoluminescence (RTPL) 6,7 measurements. Figure 1 shows the flow of Si wafer inspection and process steps.…”

Investigation of Plasma Enhanced Chemical Vapor Deposition Chamber Mismatching by Photoluminescence and Raman Spectroscopy

“…Multiwavelength RTPL intensity P317 measurements of SiO 2 /Si wafers showed very promising features as a non-contact optical characterization technique for probing electrical properties of dielectric/Si structures. [16][17][18][19][20][21][22][23] The chamber-to-chamber RTPL intensity comparisons between the qualified chamber (Chamber B-1) and disqualified chamber (Chamber A) showed ∼20% reduction. The gas flow pattern change within the qualified chamber (Chamber B-1 and B-2) showed how gas flow impacts SiO 2 thickness distribution and RTPL intensity distribution on Si wafers.…”

Noncontact Monitoring of Activation and Residual Damage of Dual Implanted Silicon Using Room Temperature Photoluminescence

“…In blanket Si wafers, RTPL measurement from the one side of the wafer can detect the anomalies on the other side of wafer, which is 775 μm away. 13 Figures 3a∼3d show RTPL spectra of wafers annealed in the temperature range of 350-800…”