Digital Signal Processing (DSP) devices are becoming increasingly important with the introduction of multiple signal processing techniques. Vedic Multiplier is one of the most common applications for high-speed DSP deployment. This paper constitutes a significant development in the design of the FIR filter architecture based on the modified Nikhalam Sutra Vedic multiplier. In addition, the Kongestone adder is used to increase speed performance. Using Xilinx FPGA Spartan 6 with Xilinx ISE, the modified architecture of FIR filter has been simulated and synthesized for achieving optimized results. The simulation results of the proposed FIR filter architecture illustrate that it operates at least 20 percent faster than traditional multiplier-based FIR filters
Over the past few decades, advances in IC technology have steadily shrunk feature sizes, necessitating the placement of more operational circuits on every chip. In designing digital circuits, a novel GDI based circuit is indeed the center of consideration, since it requires less power and achieves greater efficiency. GDI-based circuits mimic CMOS transistors but feature fewer transistors with a greater capacity for performance and reliability. This paper investigates the modelling and implementation of a Finite Impulse-Response (FIR) block developed utilizing GDI-based circuits as well as basic blocks. In this study, an eight-tap FIR architecture relying on GDI cells is created. The results reveal that even a FIR architecture with eight taps and GDI delivers reduced power consumption and performance improvement.
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