Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming

Pasuluri, Bindu Swetha; Sonti, V.J.K. Kishor

doi:10.1007/978-981-15-1420-3_114

Cited by 4 publications

(1 citation statement)

References 3 publications

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“…The method of arithmetic adder (6) and multiplexer based half adder with modified full adder (7) is used for improvement in delay of Vedic UT multiplier. The performance of Vedic multiplier (8) and divider along with convolution in DSP (9) is implemented on reconfigurable hardware. The method of Nikhilam Navatashcaramam Dashatah (10) with the algorithm and flow chart for software implementations are proposed.…”

Section: Introductionmentioning

confidence: 99%

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Sayyad,

Agarkar

2023

IJST

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Objectives: Speed of multiplication in Digital Signal Processing (DSP) applications plays an important role in generating the result quickly. There is scope for reducing the propagation delay in multiplication by designing the multiplier circuit based on the Vedic mathematics (formulas) sutras. This study aims to design the multiplier circuit based on Nikhilam Navatshcaramam Dashath (NND) of Vedic mathematics for improvement in speed, power, and area. Methods: The multiplier circuit based on NND method is designed for the multiplier and multiplicand less than as well as greater than the nearest base in the binary number system. The architecture is designed for both. The proposed multiplier is implemented with VHDL on Vertex-7, Device: XC7VX485T Package: FFG1157, FPGA board using Xilinx ISE 14.7, and its power dissipation is calculated using XPower analyzer. The performance of the proposed multiplier is compared with the conventional array multiplier, Vedic multiplier and also compared with the architecture reported in the literature. Findings: In the proposed architecture n bit multiplier and multiplicand are divided into n/2 bits, two parts, and processed through n/2 bit multiplier and n bit adder. This method converted the n bit multiplication into n/2 bit multiplication and n bit addition. The proposed architecture is efficient in terms of area, delay and power as compared to the array and Vedic Urdhva Tiryakbyham (UT) multiplier. The 4 bit NND multiplier is 26.72 % delay and 47.05 % area efficient as compared to the reported architecture (1) . To compare with other reported architecture, the results are also taken on Artix-7, Device: XC7A100T Package: CSG324, and Spartan-6, Device: XC6SLX4 Package: TQG144 FPGA. The results demonstrate an improvement in processing speed as well as power consumption. This method is a special case of multiplication and is efficient if the multiplicand and multiplier are close to the base value. In this implementation, the multiplier and multiplicand are split into two parts and processed; hence, the algorithm will give the correct result for a specific range of multipliers and multiplicands. The accuracy analysis of the proposed multiplier is also performed for multipliers and multiplicands far away from the base value. The maximum error is 7.94%. Novelty: The architecture used in this system converts n-bit multiplication into n bit addition and https://www.indjst.org/

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Section: Introductionmentioning

confidence: 99%

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Sayyad,

Agarkar

2023

IJST

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UART Implementation using the BIST Technique for Generating Test Patterns

Pasuluri

Sekhar

et al. 2021

2021 5th Conference on Information and Communication Technology (CICT)

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FPGA Implementation of Enhanced Throughput Design of AES Architecture using Nikhilam Sutra

Pasuluri

Sonti

2022

International Journal of Electrical Engineering and Computer Science

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The exponential growth of the internet and contemporary communications users have established safety as a fundamental design feature for encrypted transmission. The Enhanced Cryptography Standard is perhaps the most widely used cryptography information security algorithm standard that has been authorized by NIST. This paper proposes a high-throughput design for the AES Algorithm with huge key sizes. AES would be a block cipher that ensures data security by using key lengths of 128,192 and 256-bits. The design concept focuses on a 256-bit key size classification algorithm since a big key size is required to ensure excellent security. Additionally, simultaneous key expansion & encryption/decryption processes would be pipelined to maximize speed. Parallelization of a key expansion module's sub-processes would be used to reduce the critical chain latency. The S-box comprising sub-byte & inverse sub-byte operations has been developed with compound field arithmetic operations to reduce time and area further. The work Increased throughput by 50%, area reduced by 34.32 %, and latency by 20% compared to the old approach with modified nikhilam sutra. Additionally, integrated AES encryption/decryption is planned and implemented on the FPGA Zed board utilizing Verilog HDL in Xilinx Vivado.

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Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming

Cited by 4 publications

References 3 publications

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

UART Implementation using the BIST Technique for Generating Test Patterns

FPGA Implementation of Enhanced Throughput Design of AES Architecture using Nikhilam Sutra

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