Design and Performance Analysis of Analog Filter and Digital Filter with Vedic Multipliers in Bio-Medical Applications

Pasuluri, Bindu Swetha; Sonti, V.J.K. Kishor

doi:10.1109/iconat53423.2022.9725831

Cited by 3 publications

(1 citation statement)

References 17 publications

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“…In other words, FIR filter algorithm implementation using a general-purpose processor running on a personal computer (PC) will not give the best performance in terms of processing speed. To speed up the processing speed, hardware implementations of the FIR filter have been proposed in many previous works [14][15][16][17][18][19][20]. Most of the designs were implemented on the FPGA as it offers flexibility in terms of reconfigurable.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

Chessda Uttraphan,

Mohd Izzul Ariffi Ardani,

Chua Wee Heng

et al. 2024

ARASET

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Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG signal. Nevertheless, the processing speed of software-based FIR filters is slow for large ECG datasets due to serial processing. This paper presents a hardware implementation of the FIR filter for ECG signal processing to overcome the processing speed issue. The filter is designed using the Kaiser Window method and implemented on the Intel Cyclone IV Field Programmable Gate Array (FPGA). The filter is first designed in MATLAB to obtain the filter coefficients where the ECG data were obtained from Physionet database. From the difference equation, we designed the signal flow graph (SDFG) and then mapped into hardware logics to enable parallel processing. Simulation results of the software (MATLAB) and hardware (FPGA) implementations are obtained and compared. The results show that the FPGA-based FIR filter can process the ECG signal up to 1,250 times faster than software implementations. To further optimize the design and reduce hardware cost, we introduce optimized designs by applying the operation scheduling and constrained resource allocation techniques. The maximum operating frequency, logic utilization, and power consumption of each design were analysed and compared. This study demonstrates that custom-designed hardware logic for digital signal processing can significantly outperform software implementations due to its parallel processing capabilities. The proposed optimization techniques reduce the hardware cost while maintaining high processing speed and accuracy. The hardware implementation of the FIR filter for ECG signal processing has numerous applications in diagnosing heart-related diseases and real-time monitoring of ECG signals in critical care settings.

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Section: Introductionmentioning

confidence: 99%

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

Chessda Uttraphan,

Mohd Izzul Ariffi Ardani,

Chua Wee Heng

et al. 2024

ARASET

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ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

Janwadkar,

Dhavse

2024

Microprocessors and Microsystems

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Design of High-performance GDI Logic Based 8-tap FIR Filter At 45nm CMOS Technology Using Nikhilam Multiplier

Pasuluri

Sonti

2022

International Journal of Mathematical Models and Methods in Applied Sciences

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Over the past few decades, advances in IC technology have steadily shrunk feature sizes, necessitating the placement of more operational circuits on every chip. In designing digital circuits, a novel GDI based circuit is indeed the center of consideration, since it requires less power and achieves greater efficiency. GDI-based circuits mimic CMOS transistors but feature fewer transistors with a greater capacity for performance and reliability. This paper investigates the modelling and implementation of a Finite Impulse-Response (FIR) block developed utilizing GDI-based circuits as well as basic blocks. In this study, an eight-tap FIR architecture relying on GDI cells is created. The results reveal that even a FIR architecture with eight taps and GDI delivers reduced power consumption and performance improvement.

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Design and Performance Analysis of Analog Filter and Digital Filter with Vedic Multipliers in Bio-Medical Applications

Cited by 3 publications

References 17 publications

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

Design of High-performance GDI Logic Based 8-tap FIR Filter At 45nm CMOS Technology Using Nikhilam Multiplier

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