With the recent proliferation of different types of Cyber Physical Systems (CPS), it is critically important to investigate the predictability of such systems. Along with functional correctness of the components, these systems must also ensure that timing and delay constraints of components are properly for the entire system to behave in a predictable manner in presence of various kinds of uncertainties. While the functional correctness of the CPS components has been investigated in the past, very little is available about the timing issues. The objective of this paper is to conduct an investigation of key issues involved to ensure the predictability of the system, introduce rigorous definitions of performance parameters, and propose metrics for their evaluation and analyze their suitability to be used in the presence of uncertainties in which CPS operate. The results are expected to provide greater insight into the time critical behavior of CPS components.
Modern multi-core processors propose new cache management challenges (more cache conflicts and misses) due to the subtle interactions of simultaneously executing processes sharing on-chip resources. To address this issue, thread group scheduling scheme that cluster threads with high sharing cache as one group to schedule has been proposed. It has led to numerous academic and industrial attentions. However, by analyzing the programming model of Android which account for a large and increasing fraction of operating system of multi-core smart phones, we find it may be unacceptable for numerous interactive applications since previous scheduling works may cause the terrible response time and directly bring an awful user experience. In order to reduce cache competitions while improving application's response time, we present an application-aware group scheduler (AGS) whose key idea is to adopt a thread group scheduling scheme to partition current running application's threads into one group and give each thread a fair chance to occupy CPU time. We implement AGS on practical hardware running a real Android operating system. The results show that our proposed scheduler can improve performance from different parameters while keeping system fairness, which reduces 3.2% in cache miss rate, 5.5% in response time, 5.3% in data cache (D-Cache) misses and 2.5% in instruction cache (I-Cache) misses to the maximum extent.
Performance of software is increasingly restricted by the Memory Wall instead of CPU. Many studies focus on alleviating the DRAM latency by improving the row-buffer hit rate. But most of them treat the Kernel 1 and User 2 equally. Data used by Operating System and User applications spread in different rows of the same bank, leading to the contentions for the row-buffer when they access the bank successively. We find that contentions between Kernel and User make up of a great proportion of all the row-buffer misses. To alleviate the contentions between Kernel and User, we divide the united DRAM memory space into Kernel-Space and User-Space. A new page-allocation-system, the K/U-Aware page-allocation-system, is proposed to manage Kernel-Space and User-Space in DRAM memory in different address mapping schemes of DRAM memory controller. In the new system, pages are allocated from different spaces according to applicants (Kernel or User). Sizes of the two spaces increase and decrease dynamically as required. For benchmarks in PARSEC suites, the proposed system reduces the contentions of Kernel and User effectively, producing significant improvements of row-buffer hit rate. The execution time is reduced by 9.45% (max. 20.45%) and 6.51% (max. 18.05%) respectively in two typical address mapping schemes.
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