We propose an on-current (above threshold voltage) model of polycrystalline silicon thin-film transistors (poly-Si TFTs). The model includes the study of the effect of trap state density, poly-Si inversion layer thickness and temperature on the TFT characteristics. Effective carrier mobility and I-V characteristics are described by considering the mechanism of capture and release of carriers at grain boundary trap states and the thermionic emission theory. It is found that at low as well as at high doping concentrations, the effective carrier mobility (µeff) increases with increasing temperature whereas a dip is observed at intermediate doping concentration. At very high and very low doping concentration the effect of temperature on the mobility is found to be almost negligible. Calculations reveal that effective carrier mobility and drain current increase as the gate bias increases and are larger for a lower trap state density. The calculated value of activation energy decreases as the gate bias increases and is larger for a larger poly-Si inversion layer thickness. A comparison between the present predictions and the experimental results shows reasonably good agreement.
Theoretical investigations of the influence of grain size (D) and doping density (NA), on the carrier concentration (p*) and effective resistivity (ϱ*) of polycrystalline silicon are made, considering the finite thickness (2t) of the grain boundary region and the dynamics of capture and release of carriers at the grain boundary trap‐states. It is found that for low values of impurity concentration the average carrier concentration (p*) and the effective resistivity (ϱ*) are controlled by trapping of free carriers at the grain boundary trap‐states where, as for higher doping densities, the values of p* and ϱ* tend to those of a single crystal as a result of saturation of the trapping states.
Influence of the grain size on the effective carrier mobility (μeff) and transfer characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT) has been theoretically investigated by developing an analytical model. The dependence of μeff is studied as function of doping concentration and gate voltage for different values of grain size. It is observed that at low as well as at high doping concentrations, the effective carrier mobility (μeff) increases with increasing grain size, whereas the observed dip at the intermediate doping concentration is confirmed. The effect of the grain size on transfer characteristics of poly-Si TFT in its linear region is also presented. It is found that at low gate voltages, μeff and ID increase rapidly with the increase in VG for all grain sizes due to the grain boundary barrier lowering effect. At high gate voltage the grain boundary barrier lowering effect becomes insignificant and causes the saturation of μeff and ID. The model was found to account correctly for the experimentally observed mobility variation and yield a reasonably good agreement.
The increase in diode quality factor with decreasing grain size in polycrystalline conductor (metal or degenerate semiconductor)-insulator-semiconductor (MIS) solar cells is explained as due to (1) an increase in insulator-semiconductor interface charge due to the presence of grain boundaries on the I-S surface, and (2) the voltage drop at the grain boundaries in the polycrystalline base semiconductor.
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