In this abstract we present a highly manufacturable, high performance 90nm technology with best in class ,performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uAium and 587uAium are obtained for nMOS and PMOS transistors respectively at I .2V Vdd and an Ioff of 60nMpm. An industry leading 90nm technology CVil of 0 . 6 1~s and 1 .
As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.
Characterization of metal-insulator-metal (MIM) capacitors with a scaled dielectric is a challenge using conventional capacitance-voltage (C-V ) measurements due to a high leakage current. In this letter, a method to analyze MIM capacitance that is more immune to the leakage current problem has been successfully demonstrated using time domain reflectometry (TDR). The TDR method can be applied to Al 2 O 3 MIM capacitors with a capacitance density up to ∼11.1 fF/µm 2 , for which an impedance analyzer has failed to measure capacitance at 1 MHz. Differences in the voltage coefficient of capacitance and dielectric constant (k) were also investigated.Index Terms-Capacitance, metal-insulator-metal (MIM) capacitor, time domain reflectometry (TDR), voltage coefficient.
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