The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO 2 at expected operating voltages. The results of SiO 2 /alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO 2 thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO 2 on the current characteristics of the dielectric stack increases. Semiconductor Research Corporation (SRC Contract 132).

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In this abstract we present a highly manufacturable, high performance 90nm technology with best in class ,performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uAium and 587uAium are obtained for nMOS and PMOS transistors respectively at I .2V Vdd and an Ioff of 60nMpm. An industry leading 90nm technology CVil of 0 . 6 1~s and 1 .

Articles you may be interested inInvestigation of roughened silicon surfaces using fractal analysis. I. Twodimensional variation method Selective epitaxial growth with oxidepolycrystalline siliconoxide masks by rapid thermal processing chemical vapor deposition Fractal analysis was applied to images of rough silicon surfaces which were acquired with an atomic force microscope. Spectroscopic ellipsometry was also used to extract roughness information using an optical model and the Bruggeman effective-medium approximation. Different rough silicon surfaces were examined from three microelectronics processes; rapid thermal chemical vapor deposition, chemical etching, and thermal oxidation. The fractal nature of the surfaces and the correlation between fractal, optical, and topographic parameters were explored.

Deposition of undoped and in situ boron-doped polycrystalline silicon-germanium (poly-Si1−xGex) films on oxide has been investigated at temperatures below 625 °C and a pressure of 4 Torr in a rapid thermal chemical vapor deposition system. The influences of reactant gases such as Si2H6, SiH4, GeH4, and B2H6 on the nucleation behavior, and structural properties of poly-Si1−xGex films formed on oxide were studied. The experimental results showed that in situ boron-doped or undoped poly-Si1−xGex films can be directly deposited on oxide without an initial Si predeposition layer to provide the necessary nucleation sites on the surface when using Si2H6 as the Si source gas. However, when SiH4 was used as the Si source gas, only in situ boron-doped films can be deposited nonselectively on the oxide without the initial Si predeposition layer, and to deposit undoped poly-Si1−xGex films, Si predeposition is needed, otherwise Si1−xGex islands are formed on the oxide. X-ray diffraction analysis showed that poly-Si1−xGex films deposited using Si2H6, GeH4, and B2H6 gas mixture have three singular peaks corresponding to {311}, {220}, and {111} planes, thus indicating the Si1−xGex alloy is formed. In addition, we found that B2H6 gas has a minor effect on the Ge incorporation into the films but reduces the overall deposition rate.

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A reliability assessment methodology consisting of a statistical model and experiments to evaluate the leakage mechanism responsible for Low Temperature Data Retention (LTDR) in floating gate non-volatile memories is presented. The nature of the leakage mechanism and the methodology necessary to observe and accurately assess this phenomenon are described.

This paper describes the preparation of silicon-based metal oxide semiconductor, MOS, devices, capacitors and field effect transistors, FETs, using deposited oxide dielectrics. A critical aspect of the device fabrication process is the way the Si-SiO2 interface is formed; e.g., either before, during, or after the oxide deposition. We have studied different methods of fabricating Si-SiO2 heterostructures, and have concluded that the implementation of independently controllable and sequential process steps for (i) interface formation, and (ii) oxide deposition consistently yields MOS devices with electrical properties that are superior to those of devices fabricated under other processing conditions which include specifically interface formation during the oxide deposition.