Device instabilities of graphene metal-oxide-semiconductor field effect transistors such as hysteresis and Dirac point shifts have been attributed to charge trapping in the underlying substrate, especially in SiO2. In this letter, trapping time constants around 87 μs and 1.76 ms were identified using a short pulse current-voltage method. The values of two trapping time constants with reversible trapping behavior indicate that the hysteretic behaviors of graphene field effect transistors are due to neither charge trapping in the bulk SiO2 or tunneling into other interfacial materials. Also, it is concluded that the dc measurement method significantly underestimated the performance of graphene devices.

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The benefits of multi-layer graphene (MLG) capping on Cu interconnects have been experimentally demonstrated. The resistance of MLG capped Cu wires improved by 2-7% compared to Cu wires. The breakdown current density increased by 18%, suggesting that the MLG can act as an excellent capping material for Cu interconnects, improving the reliability characteristics. With a proper process optimization, MLG capped Cu interconnects could become a promising technology for high density back end-of-line interconnects.

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The feasibility of a high speed ferroelectric graphene memory device using a ferroelectric polymer (PVDF-TrFE)/graphene stack has been demonstrated. The conductivity of this metal-ferroelectric-graphene (MFG) device could be modulated up to 775% with a very fast programming speed down to 10 ns. Also, programmed states were maintained up to 1000 s with endurance over 1000 cycles. In addition to demonstrating a single memory device, the array-level integration and cell write/read functionality of a 4 × 4 MFG array adopting a graphene bit line has also been confirmed to show the feasibility of MFG memory.