A self-aligned complementary GaAs (CGaAs TM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01µW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC TM-architecture microprocessor. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application of the CGaAs technology.
We present the results of a Monte Carlo calculation of the electron velocity and mobility, as well as mobility measurements in compensated GaAs. For appreciable compensation ratios, the peak velocity, negative differential mobility, and peak-to-valley velocity ratios are drastically reduced in comparison with those in uncompensated GaAs. This reduction makes the Gunn effect less likely to manifest itself in ion-implanted GaAs metal-semiconductor field-effect transistors and other GaAs devices where compensation is important.
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