No abstract

No abstract

No abstract

Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybridintegrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4V pp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for opticaldynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.As seen in Fig. 22.6.1, wire-bonding-based hybrid integration provides a low-cost approach for Si-photonic systems with a moderate number of pads. The Si-photonic WDM chip in this work consists of 8 common bus MRMs [1], with 5 of them wire-bonded to the CMOS transmitter IC. The measured DC ring spectrum data of the MRMs, which have a 7.5μm radius and ~5000 quality factor, shows that 4V swing is required to achieve >7dB extinction ratio. One potential approach to achieve this large swing amplitude involves the use of differential pulsed-cascode output stages using thin-oxide transistors [3,4], which can achieve 2×DVDD swing per-terminal, or an effective 4×DVDD differential swing on the modulator. However, DC-coupled differential drivers can provide only a 0V DC-bias, which conflicts with the negative-bias requirement for depletion-mode operation. While adding negative supply voltages can provide fixed DC-biases for the differential outputs [2], the number of power-supply domains will increase. In this work, an AC-coupled differential output stage is developed that enables 4×DVDD swing together with a tunable negative DC-bias. Figure 22.6.1 shows the on-chip DC-blocking capacitor C C and DC-bias resistor R B , implemented with the pulsed-cascode output stages to decouple the high-frequency modulation from the DC-bias voltages. The insertion loss of the driver passive network is designed to be <1dB between 0.1 and 20GHz, to minimize signal-integrity degradation and achieve ~4.4V pp-diff effective output swing from a 1.2V DVDD supply. Figure 22.6.2 shows the block diagram of the 5-channel transmitter array. A half-rate global clock is distributed through an on-chip transmission line and locally recovered by per-channel CML-to-CMOS converters. 8-to-1 data serialization is achieved using three stages of CMOS MUXs. In conventional high-speed 2-to-1 MUX designs, retiming latches are used to introduce 1-UI de...

Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1][2][3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity. Figure 22.4.1 shows a hybrid-integration WDM receiver, with the silicon photonic IC with microring drop filters and waveguide photodetectors connected via short wirebonds to the CMOS receiver IC with the developed optical front-end circuits. Here the microring drop filters share a common bus waveguide and select a given wavelength per channel to direct onto a waveguide photodetector. In order to allow for low-complexity receive-side clocking, we develop a source-synchronous architecture with an optically forwarded clock from the WDM transmitter on one of the available wavelengths. The microring drop filters used in this work have 5μm radius and 18000 quality factor, while the waveguide photodetectors have 40fF capacitance, 0.45A/W responsivity, and 30GHz bandwidth. While this hybrid integration strategy allows for independent optimization of the photonic devices and CMOS circuits, it does add potentially a wide range of interconnect parasitics that must be compensated for in the optical front-end design.The CMOS optical receiver chip shown in Fig. 22.4.2 consists of one forwardedclock receiver channel that provides a synchronous 12GHz differential clock to the four data channels. While previously an optically-forwarded clock receiver was demonstrated at 8Gb/s with an injection-locked ring oscillator [3], at data-rates in excess of 20Gb/s the wideband clock receiver input-referred noise can induce unacceptable output jitter that is not sufficiently filtered with a wide-bandwidth ring oscillator. This design utilizes a 12GHz LC injection-locked oscillator, which allows for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Simulations show that a 12GHz 40μA inp...

No abstract

ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1][2][3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer. Figure 3.6.1 shows PAM2 BER bathtub curves for two backplane channels with different attenuations. The low-loss channel has an open eye with a voltage region over which a two-level slicer can reliably detect both '0' and '1' symbols at the required BER. Increased ISI from the high-loss channel causes the received eye to close with a slicer threshold set at the nominally optimal zero level, where significant errors are observed. In this case, typical receivers employ equalization on all received symbols to reduce ISI and open the eye to achieve the target BER. Certain received signal levels, however, have a very low probability of generating an error for a given symbol and do not necessarily require additional equalization. Our hybrid ADC-based receiver takes advantage of this to save power by employing a three-level detector with programmable thresholds that allows for reliable detection of both '0' and '1' symbols when the received signal falls outside the ambiguous region, and dynamically disables the digital equalizer on a per-symbol basis. For symbols in the ambiguous region that cannot be reliably detected, the digital equalizer is dynamically enabled to further remove ISI and achieve the target BER. Combining this technique with embedded FFE in the ADC allows for a significant reduction in digital equalizer power. The embedded FFE reduces the percentage of symbols in the ambiguous region [4].The hybrid ADC-based receiver utilizes a 32-way time-interleaved 6b SAR ADC with embedded 3-tap FFE, as shown in Fig. 3.6.2. This 10GS/s converter has eight parallel sub-ADCs, each consisting of a front-end T/H clocked at 1.25GHz followed by four asynchronous unit SAR ADCs. A differential divide-by-four circuit is used with 5GHz complementary input clocks to generate the eight phases spaced at 100ps that clock the sub-ADC T/Hs. Digitally controlled capacitor banks, with a <0.4ps resolution and ~30ps range, are employed to calibrate timing mismatches in the clock distribution to the T/H blocks. The ADC includes calibration DACs for comparator offset, linear gain, and sampling clock skew. A switched-capacitor implementation allows for efficient embedding of the 3-tap FFE, which i...

No abstract