Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

Li, Cheng; Bai, Rui; Shafik, Ayman; Tabasy, Ehsan Zhian; Wang, Binhao; Tang, Geng; Ma, Chao; Chen, Chin‐Hui; Peng, Zhen; Fiorentino, Marco; Beausoleil, Raymond G.; Chiang, Patrick; Palermo, Samuel

doi:10.1109/jssc.2014.2321574

Cited by 94 publications

(43 citation statements)

References 33 publications

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“…However, as is shown in Fig 1(c) [8], it has been demonstrated that a cascaded push-pull driver can supply a large output swing without using a external biasing network. However, the low speed PMOS transistor in the top of output stage always limits the driver's speed of operation, and the two independent pre-drivers have to be created at different voltage level for the top and bottom input signals (Vin_high and Vin_low).…”

Section: A Design Conceptmentioning

confidence: 99%

“…Not only because of critical design specifications in bandwidth, voltage swing and power consumption, but also due to the requirement of a high density, low cost integration approach. As shown in Fig 1, previous recent work has demonstrated silicon photonic transmitters with a frontend based on a vertical cavity surface emitting laser (VCSEL) [9], ring resonator modulator(RRM) [8] and Mach-Zehnder modulator (MZM) [2][4] [7]. Although the MZM approach has lower power efficiency compared to other two approaches [6], the relatively large bandwidth and improved tolerance to process and temperature variation make it attractive for low cost silicon photonic transceivers.…”

Section: Introductionmentioning

confidence: 99%

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A 30 Gb/s CMOS driver integrated with silicon photonics MZM

Thomson

Liu

et al. 2015

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Abstract-A voltage mode modulator driver is proposed in the TSMC 65nm low power CMOS process. In the electrical testing, the driver itself can achieve a bit rate of 40Gb/s with the single-ended output swing of 1.65V. Unlike equivalent CML modulator drivers, when the proposed driver is integrated with the silicon photonic MZM, it does not require an additional biasing network. The integrated electro-optic transmitter can achieve 30Gb/s with an extinction ratio of 4.05dB, with the power consumption of main driver being 323mW.Index Terms-modulator driver, silicon photonics, MachZehnder Modulator (MZM), power amplifiers.

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Section: A Design Conceptmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 30 Gb/s CMOS driver integrated with silicon photonics MZM

Thomson

Liu

et al. 2015

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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“…The brute-force BER testing method is unaffordably time-consuming (over 100 seconds for 10 −12 BER at 10Gbps data rate) for the proposed adaptive tuning. Fortunately, there are fast BER estimation methods that leverage voltage offsetting or sampling time offsetting [28], [29]. As illustrated in Fig.…”

Section: Adaptive Tuning Approachmentioning

confidence: 99%

“…The hardware overhead, mainly in the BER monitor, includes an additional comparator with offset control and a small logic circuit, which takes about 30 µm x 30 µm area for a 65 nm CMOS technology [28]. For a multi-receiver link, its hardware cost can be amortized by sharing the BER monitor, as the multiple receivers on one link cannot receive signal simultaneously.…”

Section: Adaptive Tuning Approachmentioning

confidence: 99%

Variation-aware adaptive tuning for nanophotonic interconnects

Wu¹,

Chen²,

Li³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Short-reach nanophotonic interconnects are promising to solve the communication bottleneck in data centers and chip-level scenarios. However, the nanophotonic interconnects are sensitive to process and thermal variations, especially for the microring structures, resulting in significant variation of an optical link's bit error rate (BER). In this paper, we propose a power-efficient adaptive tuning approach for nanophotonic interconnects to address the variation issues. During the adaptive tuning process, each nanophotonic interconnect is adaptively allocated just enough power to meet the BER requirement. The proposed adaptive tuning approach could reduce the photonic receiver power by 8% -34% than the worst-case based fixed design while achieving the same BER. Our evaluation results show that the adaptive tuning approach scales well with the process variation, the thermal variation and the number of communication nodes, and can accommodate different types of NoC architectures and lasers.

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“…For instance, in silicon (Si) photonic devices, such as microring resonators (MRRs), control issues become even more critical because of the wavelength selectivity of the MRR response and the high temperature dependence of the Si waveguides [10][11][12][13][14][15]. When managing architectures integrating many MRRs [16][17][18], it is challenging to identify the current resonant wavelength of each MRR in order to tune and lock their spectral response to the wavelengths of the incoming optical signals.…”

mentioning

confidence: 99%