It is well known that organic thin film transistor (OTFT) parameters can be shifted depending on the geometry of the device. In this work, we present two different transistor geometries, interdigitated and Corbino, which provide differences in the key parameters of devices such as threshold voltage (VT), although they share the same materials and fabrication procedure. Furthermore, it is proven that Corbino geometries are good candidates for saturation-mode current driven devices, as they provide higher ION/IOFF ratios. By taking advantage of these differences, circuit design can be improved and the proposed geometries are, therefore, particularly suited for the implementation of logic gates. The results demonstrate a high gain and low hysteresis organic monotype inverter circuit with full swing voltage at the output.
Organic Devices offer low-cost manufacturing and better flexibility, sustainability and solution-processability than their Si-based MOS counterparts, which make them suitable for new applications where those characteristics are an advantage. However, organic device performance is still far from that provided by CMOS technology and many issues are still unclear. In this work, a performance comparison of Interdigitated and Corbino geometries of Organic Thin Film Transistors (OTFT), with different areas but fabricated with identical stack materials and techniques, is done. With this purpose, I-V characteristics and C-V curves of the OTFTs were measured and a Common-Source circuit was proposed and implemented for extracting relevant electrical parameters of the devices, through a standard small signal analysis. The parameter extraction methodology in the frequency domain proposed allows rapid testing of the device/circuit performance of this technology, which is for the first time applied to organic devices. Results show that organic transistors exhibit similar channel dimensions dependencies as MOS devices, despite the large voltages, and can be also described by the same small signal model.
Organic and printed electronics (OE) is a promising technology for reducing the waste and the price of electronic systems for new devices. OE offers technological advantages not available in conventional silicon processes such as physical flexibility, large area fabrication, mask-less deposition, low process temperatures and fully additive manufacturing-processes that all enable low-cost and low-waste fabrication techniques. Despite these advantages, important difficulties remain for developing compact models for transistors due to intrinsic variability in the manufacturing process and the behaviour of organic materials, which make it difficult to match the model and the experimental data. Due to disparity in the fabrication methodologies and the different topologies of transistors used, the diversity in compact models is noticeable. These different models provide specific solutions for particular devices and require various process design kits (PDKs) for each manufacturing process. This review covers the different PDKs developed in the OE field and compares them with the electric models used for simulation purposes. Both simulated and fabricated systems are included with the aim of providing the reader with a clear state-of-the-art of the OE situation.
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