TFT backplane process for AM‐OLED was developed by integrating a G8 compatible CW green laser annealing into conventional bottom‐gate TFT process. Novel coating channel‐etching‐stopper (CES) and contact doping processes achieved the same high TFT performance as LTPS without critically increasing extra process steps.
We developed and fabricated self-aligned bottom gate LTPS backplanes without ion-implantation process. CW green laser is used to fabricate polycrystalline silicon, and self-alignment photo-sensitive SiO coating film is used as a channel etch stopper. For high performance TFT backplanes, we developed CMOS process that allows us to operate CMOS circuits. Our developed TFT shows high mobility and high reliability.Author Keywords thin film transistor (TFT); low temperature polycrystalline silicon (LTPS); CW laser; self-aligned; bottom gate; back side exposure 1.
We developed double-crystalline silicon channel thin film transistors (TFTs) whose active region consisted of a polysilicon layer and a microcrystalline silicon layer. The polysilicon layer was formed by continuous-wave green laser annealing with scalability to large substrates. The microcrystalline silicon layer formed on the polysilicon layer provides a sufficient channel etching margin for the fabrication of TFTs on large substrates without degradation of TFT mobility. The kink-free output characteristics were realized by a band-gap engineering method using a microcrystalline silicon layer. The TFT characteristics desirable for organic light-emitting diode display applications, namely, high mobility, high reliability, and kink-free output characteristics, have been successfully demonstrated.
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