P‐12: Self‐Aligned Bottom Gate LTPS Backplanes without Ion‐Implantation Process

Abstract

We developed and fabricated self-aligned bottom gate LTPS backplanes without ion-implantation process. CW green laser is used to fabricate polycrystalline silicon, and self-alignment photo-sensitive SiO coating film is used as a channel etch stopper. For high performance TFT backplanes, we developed CMOS process that allows us to operate CMOS circuits. Our developed TFT shows high mobility and high reliability.Author Keywords thin film transistor (TFT); low temperature polycrystalline silicon (LTPS); CW laser; self-aligned; bottom gate; back side exposure 1.

Bottom gate single crystal Si thin-film transistors fabricated by all sputtering processes

“…Although LTPS top-gate TFTs (TG-TFTs) have been widely applied for driving OLEDs, BG TFTs are also in high demand because of their compatibility with fabrication process of a-Si BG-TFTs. Several groups have proposed LTPS BG-TFTs in which a-Si precursor films are crystallized by either excimer laser crystallization (ELC), [6][7][8][9] or cw laser crystallization (CLC), 10,11,12) However, the uniformity of TFTs is also an important issue for high-definition displays because the variation of grain numbers in the channel region causes characteristic deviation of TFTs. Single-crystal Si (c-Si) TFTs provide the ultimate solution to this challenge.…”

P‐196: Late‐News Poster: Off Current Reduction of BG poly‐Si TFT by PLAS Process

“…However, in the case of poly-Si, when using a laser annealing technique such as Excimer Laser Annealing (ELA), which is necessary for polycrystallization of a-Si, it is difficult to increase the glass size due to the limitation of the line beam length [3]. Also, the Low Temperature Poly-Silicon (LTPS) thin-film transistor (TFT) process has a higher cost than a-Si TFT structure because it requires ELA and ion implantation steps [4]. When using oxide TFT, it is difficult to control the reliability because of its low photo-stability.…”

Novel LTPS technology for large substrate

“…Hence, it is too difficult for the factory of large substrate such as Gen10 to adopt the high‐mobility TFT process. Several studies reported about bottom gate LTPS TFT without LDD, which showed that α‐Si layer covering with poly‐Si was used in place of LDD. And the poly‐Si did not directly contacted with source and drain metal.…”