15.4: Backplane Process Technology for AMOLEDs with Bottom‐Gate TFTs and Laser Annealing

Abstract

TFT backplane process for AM‐OLED was developed by integrating a G8 compatible CW green laser annealing into conventional bottom‐gate TFT process. Novel coating channel‐etching‐stopper (CES) and contact doping processes achieved the same high TFT performance as LTPS without critically increasing extra process steps.

Double-Crystalline Silicon Channel Thin Film Transistors Fabricated Using Continuous-Wave Green Laser for Large Organic Light-Emitting Diode Displays

“…The details of the developed crystallization technology by cw green laser annealing are described elsewhere. 8,10,11) After hydrogen plasma treatment, the microcrystalline silicon layer (c-Si) and amorphous silicon layer (a-Si) were successively formed on the polysilicon layer by PECVD. The thickness of the microcrystalline silicon layer was varied from 10 to 100 nm, while that of the amorphous silicon layer was varied from 10 to 30 nm.…”

“…The target of our project is to develop bottom-gate LTPS TFT backplanes for OLED displays, which can be more easily expanded for application to large substrates. [8][9][10][11] To achieve this target, novel TFTs having a double-crystalline silicon channel structure consisting of a polysilicon layer and a microcrystalline silicon layer as the active region were developed. To realize the fabrication on large substrates, we used the cw green laser annealing process to form the polysilicon layer.…”

Novel LTPS technology for large substrate

“…Hence, it is too difficult for the factory of large substrate such as Gen10 to adopt the high‐mobility TFT process. Several studies reported about bottom gate LTPS TFT without LDD, which showed that α‐Si layer covering with poly‐Si was used in place of LDD. And the poly‐Si did not directly contacted with source and drain metal.…”

67-1: Novel LTPS Technology for Large Substrate

“…Hence it is too difficult for the factory of large substrate such as Gen10 to adopt the high mobility TFT process. Several studies reported about bottom gate LTPS TFT without LDD [4][5][6] , which showed D-Si layer covering with poly-Si was used in place of LDD. And the poly-Si didn't directly contacted with source and drain metal.…”