Charge configuration memory (CCM) device operation is based on the controllable reconfiguration of electronic domains in a charge-density-wave material. Since the dominant effect involves the manipulation of electrons rather than atoms, the devices can display sub-picosecond switching speed and ultralow, few femtojoule switching energy. The mechanisms involved in switching between domain states of different electrical resistances are highly non-trivial and involve trapping non-equilibrium charges within topologically protected domain states. Here, we discuss the underlying physics that are deemed essential for the operation of CCM devices, focusing on the unusual asymmetry between non-thermal “write” processes and thermal “erase” processes from the point of view of the mechanism in relation to the thermal dynamics.

Current trends in data processing have given impetus for an intense search of new concepts of memory devices with emphasis on efficiency, speed, and scalability. A promising new approach to memory storage is based on resistance switching between charge-ordered domain states in the layered dichalcogenide 1T-TaS 2 . Here we investigate the energy efficiency scaling of such charge configuration memory (CCM) devices as a function of device size and data write time τ W as well as other parameters that have bearing on efficient device operation. We find that switching energy efficiency scales approximately linearly with both quantities over multiple decades, departing from linearity only when τ W approaches the ∼0.5 ps intrinsic switching limit. Compared to current state of the art memory devices, CCM devices are found to be much faster and significantly more energy efficient, demonstrated here with two-terminal switching using 2.2 fJ, 16 ps electrical pulses.

Progress in high-performance computing demands significant advances in memory technology. Among novel memory technologies that promise efficient device operation on a sub-ns timescale, resistance switching between charge ordered phases of 1 T-TaS2 has shown to be potentially useful for development of high-speed, energy efficient nonvolatile memory devices. Measurement of the electrical operation of such devices in the picosecond regime is technically challenging and hitherto still largely unexplored. Here, we use an optoelectronic “laboratory-on-a-chip” experiment for measurement of ultrafast memory switching, enabling accurate measurement of electrical switching parameters with 100 fs temporal resolution. Photoexcitation and electro-optic sampling on a (Cd,Mn)Te substrate are used to generate and, subsequently, measure electrical pulse propagation with intra-band excitation and sub-gap probing, respectively. We demonstrate high contrast nonvolatile resistance switching from high to low resistance states of a 1 T-TaS2 device using single sub-2 ps electrical pulses. Using detailed modeling, we find that the switching energy density per unit area is exceptionally small, [Formula: see text] 9.4 fJ/ μm2. The speed and energy efficiency of an electronic “write” process place the 1 T-TaS2 devices into a category of their own among new generation nonvolatile memory devices.