Polishing behavior of copper and tantalum using aqueous slurries containing alumina and silica abrasives with and without H 2 O 2 /glycine has been investigated at different pH values. It was observed that pH-dependent changes in the surface characteristics of the films being polished lead to significant variation in the copper and tantalum removal rates. Some of the surface characteristics that change with the slurry pH include the nature of the passivating layer formed on the metal surface and the hardness of such layers. It is also shown that a favorable copper to tantalum polish rate selectivity can be obtained by adjusting the slurry pH.Copper metallization is achieved by combining the single or dual damascene process with a suitable diffusion barrier layer ͑e.g., tantalum͒ with chemical mechanical planarization ͑CMP͒ to remove excess metal. For an effective application of CMP to sub-0.11 m device fabrication, a complete investigation of the polishing behavior of both copper ͑Cu͒ and tantalum ͑Ta͒ continues to be important. Significant research on Cu CMP using acidic and alkaline slurries with different oxidants and inhibiting agents has been carried out and reported in the literature, 1-20 but much less is accomplished for tantalum CMP. Most of the published polishing mechanisms for Cu and Ta polishing are based on the formation and removal of an oxidized surface layer. [1][2][3][4][5][6][7]20 demonstrated that the electrostatic interactions between the slurry particles and film surface are important during polishing. These electrostatic interactions are strongly influenced by the pH of the slurry. The effect of such interactions during the polishing of oxide and nitride films using silica, ceria, and alumina slurries was investigated by Hegde and Babu. 21 However, the nature and the properties of the oxidized surface layer for Cu vary with changes in the chemistry and the pH of the slurry. Cu forms a variety of oxides and hydroxides depending upon the pH, the potential at the Cu/slurry interface, and the kinetics of the surface reactions, [9][10][11]22 making it difficult to predict the role and impact of electrostatic interactions during copper polishing. Ta is inert due to the formation of a passive layer of tantalum pentoxide (Ta 2 O 5 ) which is stable at all pH values, 23 even though partial dissolution or weakening of such layers in an alkaline pH regime, with and without oxidizers, has also been reported. [24][25][26][27] Various oxidizers, such as ferric nitrate ͓Fe͑NO 3 ) 3 ] 5 and nitric acid (HNO 3 ) 1 in acidic conditions, and ammonium hydroxide (NH 4 OH), 2,3 ammonium nitrate (NH 4 NO 3 ), 2,3 and ammonium chloride (NH 4 Cl) 2 in alkaline conditions, have been used for Cu CMP. Cu CMP in strongly acidic conditions leads to reduced planarization efficiency, while polish selectivity to underlying oxide is poor in alkaline regimes. Therefore, an intermediate pH range ͑pH 4-8͒ is preferred for Cu polishing. Suitable oxidizers in this pH range are hydrogen peroxide (H 2 O 2 ), 4 potassium iodate (KI...

Chemical mechanical polishing ͑CMP͒ of metal and dielectric films was performed using mixed abrasive slurries ͑MAS͒. MAS containing alumina and silica particles dispersed in deionized water were evaluated as second step slurries for Cu damascene polishing. It was demonstrated that MAS with proper selection of constituents and composition of abrasive particles can yield desired slurry/CMP characteristics. Based on the results of transmission electron microscope and particle size analysis of the abrasives in these MAS, possible reasons for the improved CMP performance are discussed.Chemical mechanical polishing ͑CMP͒ has emerged as a viable technique for planarizing metal and dielectric films for the fabrication of microelectronic devices. CMP is used to remove the overburden Cu from damascene structures and to achieve global planarization. Polishing of materials like Ta and tantalum nitride ͑TaN͒, used as a liner layer for Cu to serve as both an adhesion promoter and as a diffusion barrier in damascene patterning, has also gained importance in the recent years. Due to the vastly different mechanical and chemical properties of Cu and the barrier layer ͑Ta or TaN͒, these layers are polished sequentially in two separate steps. The main concerns in this patterning process are dishing of Cu lines and erosion of nearby areas. 1 Minimization of these phenomena in a damascene CMP process requires that the polishing be highly selective to Ta or TaN during the second step polishing. In addition, the film surface after CMP must be free of defects such as pits, microscratches, and particles.Typical slurries contain two phases, namely, liquid and solid phases even though some abrasive free slurries have been recently proposed. 2 Liquid phase consists of deionized ͑DI͒ water with additives like oxidizers, complexing agents, inhibiting agents, and surfactants. 3 Solid phase consists of abrasives, which are typically metal oxides, e.g., alumina, silica, ceria, etc. In single abrasive slurries ͑SAS͒, the solid phase consists of only one type of abrasive particle. Despite widespread use of SAS at all levels of metallization, polish rate selectivity, surface finish, and slurry stability still remain as major challenges. 4 Mixed abrasive slurries ͑MAS͒ consist of a mixture of at least two types of abrasive particles, which can be chosen from inorganic ͑alumina, silica, ceria, etc.͒ or organic ͑poly-meric resins͒ groups. 5 It has been observed that some of the problems associated with the use of SAS can be easily controlled by using MAS with proper composition and choice of constituents of the solid phase. In this paper, slurries containing alumina and silica particles dispersed in DI water at pH 4 have been studied for the second step Cu damascene polishing process. The modified abrasives in MAS are evaluated with respect to their particle size, surface morphology, and surface potential/charge. Arguments are presented to account for the improved CMP characteristics of these particles. ExperimentalChemical mechanical polishing.-Polish...

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We report on the use of mixed abrasive slurries ͑MAS͒ containing alumina and ceria abrasives for chemical mechanical planarization ͑CMP͒ of silicon dioxide and silicon nitride films for shallow trench isolation applications, extending an earlier investigation of alumina/silica MAS for the CMP of copper and tantalum films. These slurries show a polish rate selectivity between oxide and nitride films that is as high as 65 and show an excellent surface quality even without additives. Analysis of dried slurry particles using transmission electron microscopy indicates formation of a sheath of smaller ceria particles around larger alumina particles. Possible explanations and supportive arguments for the improved performance of MAS during CMP are presented based on the particle-particle and particle-film interactions.Chemical mechanical planarization ͑CMP͒ is widely accepted as an effective technique for meeting current ͑2002͒ and near future planarization requirements of the semiconductor industry. 1 Damascene and dual-damascene processing, coupled with CMP, have successfully implemented copper ͑Cu͒ interconnects in integrated circuit ͑IC͒ fabrication, 2 leading to greatly reduced resistancecapacitance ͑RC͒ delays and superior chip performance. Another important application of CMP occurs in the use of shallow trench isolation ͑STI͒ for device isolation. STI offers better dimensional control ͑trench and width͒ and greater packing density 3,4 relative to the earlier isolation achieved by local oxidation of silicon ͑LOCOS͒. Better planarity is achieved due to the elimination of local encroachment of field oxide. 5 In STI, isolation trenches are plasma etched in the silicon substrate using a thin nitride mask layer, which simultaneously acts as a stop and a capping layer. The trenches are overfilled with chemical vapor deposited ͑CVD͒ oxide. 4 As in dualdamascene patterning, the overburden oxide is removed using CMP while removing as little of the nitride as possible. Finally, the nitride is etched using hot phosphoric acid and active devices are fabricated in the exposed silicon areas. It is critical to minimize microscratching, particulate adhesion, and overpolishing during STI CMP. 4 Introduction of a thin nitride film combined with a ceria-based, highly selective CMP process for overburden oxide removal can eliminate the need for overpolish. 6,7 These highly selective ceria-based slurries, however, can generate microscratches and hence performance must be improved further for an effective application to STI CMP.Thus, an important area of current research in CMP continues to be the development of slurries that can eliminate or minimize the problems associated with the conventional CMP process. 8,9 Typically, a slurry consists of two phases, namely, liquid and solid phases. Liquid phase consists primarily of deionized ͑DI͒ water with several additives like oxidizers, complexing agents, inhibiting agents, and surfactants. Solid phase is comprised of abrasives, which are usually inorganic oxides, e.g., alumina, silica, cer...

ABSTRACTpH has a strong effect on the polish rates of copper (Cu) and tantalum (Ta) [1]. In this paper, removal rates of Cu and Ta using aqueous slurries containing alumina and silica abrasives in H2O2-glycine solution are studied at varying pH values. It is observed that variation in the Cu and Ta removal rates is a direct result of the change in surface characteristics of the films. Surface characteristics such as presence/absence of a passivating layer and hardness of such layer vary with pH and hence result in removal rate variation. It is also shown that a favorable Cu/Ta polish rate selectivity can be obtained by adjusting the pH of the slurry.

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A critical issue associated with the implementation of wafer-level three-dimensional ͑3D͒ integration is to achieve excellent bonding and thinning performance without degrading mechanical and electrical characteristics of integrated circuit ͑IC͒ chips in the 3D wafer stack. In this work, some mechanical and electrical impacts of wafer bonding and thinning processes used to fabricate 3D ICs are evaluated using patterned wafers with two-level copper interconnect test structures that included either silicon dioxide or porous low-k interlevel dielectrics ͑ILDs͒. Benzocyclobutene ͑BCB͒ ͑Cyclotene 3022-35 from Dow Chemical͒ is the adhesive used, and thinning consists of grinding, chemical mechanical polishing, and wet etching. Three procedures used to evaluate the integrity of BCB bonded and thinned wafer stacks are discussed: ͑i͒ optical inspection of the bonding interface using glass wafers with a coefficient of thermal expansion that is close to that of silicon wafers in order to check for voids, defects, and uniformity after each bonding and thinning process; ͑ii͒ four-point bending tests to quantify bond strength and to identify the weak bond interface, and ͑iii͒ electrical tests of the patterned wafers after two bonding and thinning processes and subsequent BCB removal by plasma ashing to expose the contact pads. These procedures evaluated the impacts of processing of wafer stacks without the need for interwafer interconnect processing. Some negative mechanical and electrical impacts were observed for interconnect structures that include a porous low-k ILD, while no significant changes were observed for interconnect structures with oxide ILD.Silicon back-end-of-the-line ͑BEOL͒ technology has advanced significantly in the last decade with the advent of copper/low-k damascene patterning technology, which extended the interconnect bottleneck by approximately three generations of scaling. 1,2 However, as minimum feature size goes deeper into the submicrometer regime, global interconnects will limit the performance of gigascale integrated systems even with damascene-patterned copper/low-k technology. Three-dimensional ͑3D͒ system integration is one approach to improve interconnect performance, with several analyses having demonstrated that 3D system integration can greatly reduce global interconnect delay. 1 Moreover, monolithic wafer-level 3D system integration promises increased functionality over conventional planar integrated circuits ͑ICs͒, while maintaining the cost advantage of monolithically fabricated interconnects. [1][2][3][4] One approach to 3D system integration, using low-k dielectric polymeric adhesives for wafer bonding and copper damascene processing for fabricating interwafer vias to connect the devices on stacked wafers, is discussed in this paper. 2,5-8 Benzocyclobutene ͑BCB͒ ͑Cyclotene 3022-35 from Dow Chemical͒ was selected to be the bonding adhesive, from among several low-k dielectric polymers, because of its high bond strength and high fraction of bonded area ͑nearly 100% on 200 mm wafers͒. 2,...

A three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.