Wafer Thinning for Monolithic 3D Integration

Jindal, Anurag; Lü, Jian–Qiang; Kwon, Yongchai; Rajagopalan, G.; McMahon, Jeffrey M.; Zeng, A.; Flesher, H.K.; Cale, Timothy S.; Gutmann, R.J.

doi:10.1557/proc-766-e5.7

Cited by 7 publications

(11 citation statements)

References 6 publications

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“…Via chains with specific contact resistance $5 Â 10 À6 O cm 2 were demonstrated [46] by integrating wafer-to-wafer alignment, bonding, HAR etching in inductively coupled plasma (ICP), HAR filling using CVD copper, and thinning to an etch stop. This approach has demonstrated that active devices and passive copper/low-k structures can survive this bonding process and an aggressive thinning process several times over [47], thermal cycling to 400 8C [48], liquid-to-liquid thermal shock, and autoclave tests [49,50], and that the advantageous stress-buffering features of BCB remain after bonding [50].…”

Section: Wafer-level 3d Using Adhesive Bondingmentioning

confidence: 99%

“…High-throughput processes that are able to thin 200 -mm wafers to a thickness of 100 mm have been demonstrated [47,81]. Pushing this capability to a thinner final thickness results in remaining silicon thickness being dominated by removal rate nonuniformities.…”

Section: Timed Removal Thinning Approachesmentioning

confidence: 99%

“…This can often include withinwafer nonuniformity, wafer bow, warp, total thickness variation, die-scale pattern-dependent effects (such as planarization over dicing streets), and edge effects. Although edge effects have been marginalized by assuming yield loss at the edge in the past, this trend is changing [105], and significant defects such as cracks and unsupported areas can lead to problems during wafer thinning [47].…”

Section: Wafer-scale Planaritymentioning

confidence: 99%

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Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Three-dimensional (3D) integration with interstrata vias has the potential of improving system performance while providing a platform for heterogeneous integration. Performance improvement in 3D integrated circuits (ICs) is mainly due to the reduction of interconnect length, which decreases interconnect delay and power consumption [1,2]. Small form factor is achieved in 3D ICs due to the stacking of active device layers one on top the other. A path for heterogeneous integration is realized if this stacking is done in a fashion that is back-end-of-line (BEOL) compatible, because interconnecting devices using fully fabricated wafers can reduce process incompatibilities.Approaches to 3D integration are often divided into die-level approaches and wafer-level approaches. Most often, the heterogeneous integration and small form factor advantages are obtained with die-level approaches; in addition, high performance and low manufacturing cost can be achieved with wafer-level approaches.CMP has permeated many aspects of IC processing but is particularly a dominant factor in BEOL interconnection. Copper damascene patterning has become the standard methodology for building a large number of interconnect layers in the vast majority of high-performance ICs. In 3D ICs, CMP is also critical in backside thinning, surface roughness reduction, and, in particular, feature topography control. Topography mitigation can particularly be a critical Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li

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Section: Wafer-level 3d Using Adhesive Bondingmentioning

confidence: 99%

Section: Timed Removal Thinning Approachesmentioning

confidence: 99%

Section: Wafer-scale Planaritymentioning

confidence: 99%

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Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…Of these processes, the alignment and bonding are affected most by wafer scale nonplanarity, while the back side thinning step induces wafer scale nonplanarity issues which are best addressed by a three-step thinning process which stops on a buried oxide, i.e. an SOI approach [12]. During alignment and bonding, high bonding down-force and vacuum chucks are able to compensate for reasonable wafer bow and warp but the other effects must be considered as a constraint on the 3D approach employed.…”

Section: Wafer Scale Effectsmentioning

confidence: 99%

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

Gutmann

McMahon

Lü

2005

World Tribology Congress III, Volume 2

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Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

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“…These bonding, thinning, and interconnection processes are repeated each time a wafer is added to the stack. 2,[13][14][15][16][17] In this paper, we discuss the impacts of wafer bonding and thinning processes on the mechanical and electrical properties of wafers. We use procedures designed to avoid both wafer-to-wafer alignment and interwafer processing to interconnect devices.…”

mentioning

confidence: 99%

Evaluation of BCB Bonded and Thinned Wafer Stacks for Three-Dimensional Integration

Kwon

Jindal

Augur³

et al. 2008

J. Electrochem. Soc.

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A critical issue associated with the implementation of wafer-level three-dimensional ͑3D͒ integration is to achieve excellent bonding and thinning performance without degrading mechanical and electrical characteristics of integrated circuit ͑IC͒ chips in the 3D wafer stack. In this work, some mechanical and electrical impacts of wafer bonding and thinning processes used to fabricate 3D ICs are evaluated using patterned wafers with two-level copper interconnect test structures that included either silicon dioxide or porous low-k interlevel dielectrics ͑ILDs͒. Benzocyclobutene ͑BCB͒ ͑Cyclotene 3022-35 from Dow Chemical͒ is the adhesive used, and thinning consists of grinding, chemical mechanical polishing, and wet etching. Three procedures used to evaluate the integrity of BCB bonded and thinned wafer stacks are discussed: ͑i͒ optical inspection of the bonding interface using glass wafers with a coefficient of thermal expansion that is close to that of silicon wafers in order to check for voids, defects, and uniformity after each bonding and thinning process; ͑ii͒ four-point bending tests to quantify bond strength and to identify the weak bond interface, and ͑iii͒ electrical tests of the patterned wafers after two bonding and thinning processes and subsequent BCB removal by plasma ashing to expose the contact pads. These procedures evaluated the impacts of processing of wafer stacks without the need for interwafer interconnect processing. Some negative mechanical and electrical impacts were observed for interconnect structures that include a porous low-k ILD, while no significant changes were observed for interconnect structures with oxide ILD.Silicon back-end-of-the-line ͑BEOL͒ technology has advanced significantly in the last decade with the advent of copper/low-k damascene patterning technology, which extended the interconnect bottleneck by approximately three generations of scaling. 1,2 However, as minimum feature size goes deeper into the submicrometer regime, global interconnects will limit the performance of gigascale integrated systems even with damascene-patterned copper/low-k technology. Three-dimensional ͑3D͒ system integration is one approach to improve interconnect performance, with several analyses having demonstrated that 3D system integration can greatly reduce global interconnect delay. 1 Moreover, monolithic wafer-level 3D system integration promises increased functionality over conventional planar integrated circuits ͑ICs͒, while maintaining the cost advantage of monolithically fabricated interconnects. [1][2][3][4] One approach to 3D system integration, using low-k dielectric polymeric adhesives for wafer bonding and copper damascene processing for fabricating interwafer vias to connect the devices on stacked wafers, is discussed in this paper. 2,5-8 Benzocyclobutene ͑BCB͒ ͑Cyclotene 3022-35 from Dow Chemical͒ was selected to be the bonding adhesive, from among several low-k dielectric polymers, because of its high bond strength and high fraction of bonded area ͑nearly 100% on 200 mm wafers͒. 2,...

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Wafer Thinning for Monolithic 3D Integration

Cited by 7 publications

References 6 publications

Three‐Dimensional (3D) Integration

Three‐Dimensional (3D) Integration

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

Evaluation of BCB Bonded and Thinned Wafer Stacks for Three-Dimensional Integration

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