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Portilla, J., de Castro, A., Abril, A., Riesgo, T., “Integrated hardware interfaces for modular sensor networks”, Proceedings of SPIE - The International Society for Optical Engineering”, 6590, 9, 2007. Copyright 2007. Society of Photo‑Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.Sensor networks have reached a great relevance during the last years. The idea is to use a large number of nodes measuring different physical parameters in several environments, which implies different research challenges (low power consumption, communication protocols, platform hardware design, etc). There is a tendency to use modular hardware nodes in order to make easier rapid prototyping as well as to be able to redesign faster and reuse part of the hardware modules. One of the main obstacles for rapid prototyping is that sensors present heterogeneous interfaces. In this paper, a VHDL library for sensors/actuators interfaces is proposed. The purpose is to have a set of different sensor interfaces that include the most common in the sensors/actuators world, enabling the rapid connection to a new sensor/actuator. Moreover, the concept presented here may be used for new interfaces that can be easily developed. The VHDL implementation is independent of the final platform (any FPGA or ASIC) in order to minimize redesign effort and make easier rapid prototyping. The interfaces are installed in a UPM platform for sensor networks

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In this paper, we present a high-level power macromodeling technique at register transfer level (RTL). The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) macroblocks by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

This paper proposes a method for energy consumption estimation and optimisation on hardware-software embedded systems-on-chip. The aim of our work is to provide a simulation framework enabling power estimations of high level descriptions (behavioural C models) of systems that include all the hardware components also the new ones. Such analysis are needed to select the best hardware architecture and software organization for a particular application in terms of power consumption and to apply low power techniques at system level.The starting point is the architectural description of the system used for simulation. It employs very abstract C-based models of the hardware components. We focus on the cycle-accurate level to improve the estimation accuracy. Behavioural models are extended with energy models that take into account the operations executed per transition into the state machines of the components.The method has been tested in a MPEG4 decoder implementation. The error of the energy estimations was estimated lower than 6% from physical measurements. Low power techniques were applied and analyzed like another memory hierarchy, clock gating, voltage/frequency scaling, and some others. It has permitted to reduce the consumption cost of the system on 93%.

In this paper, we present an architectural power estimation technique for register transfer level. The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.