2007 IEEE International Symposium on Industrial Electronics 2007
DOI: 10.1109/isie.2007.4374976
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Abstract: In this paper, we present an architectural power estimation technique for register transfer level. The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromode… Show more

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